URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] [log/] [pci_tb.log] - Rev 154
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************************ PCI IP Core Testbench Test results *****************************************************************************************************************At time 98835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 99300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 99735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 100200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 101595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 102165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 102825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 103515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 104175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 105700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 106300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 107700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 108300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 111300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 112000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 112635000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 113220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 113820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 114825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 115420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 117105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 117580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 118005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 118480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 119895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 120465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 121125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 121815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 122475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 124600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 126600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 129600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 130300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 130935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 131520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 132120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 133125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 133720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 135405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 135880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 136305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 136780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 138195000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 138765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 139425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 140115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 140775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 142900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 144900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 147900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 148600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 149235000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 149820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 150420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 151425000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 152020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153500000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 153700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154580000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154680000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 154880000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155240000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155360000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155480000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 155600000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158145000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158460000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158540000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 158820000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 159945000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 161080000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 161800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 162060000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 166180000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 166440000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 167880000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 168160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 169780000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 170040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 171855000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172185000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172700000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 172980000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 173260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 173520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 174435000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 174720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 175260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 175540000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 177645000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 177940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 178480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 178560000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 179320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 180060000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 180940000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181200000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 181960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 182800000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 183060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 184320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 185540000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 185820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 187080000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 187725000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188020000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 188820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 189480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 192945000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 193300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 193995000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 194340000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 194955000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 195400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196360000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196520000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 196800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 197280000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 197660000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198240000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198420000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 198700000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 199180000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200140000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 200680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 201375000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 201660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202275000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202605000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 202900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203385000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 203860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 204340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 204887000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 205840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 206920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 207400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 207885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 208840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209325000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 209800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 210280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 210975000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211160000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 211920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 212535000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 212865000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213645000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 213840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214635000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 214820000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 215100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 215580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217065000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217260000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 217540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 218020000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 218925000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219120000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 219880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 222945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223185000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223425000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 223935000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 224205000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 224445000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225075000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225315000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 225945000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 226515000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 226905000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 227625000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 227865000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 228705000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 231615000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 231885000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 232305000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 232725000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 241515000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 260520000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 261420000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 266020000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 266820000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 267520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 268660000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 270060000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 270660000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 277840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 278620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 279400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 280395000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 284080000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 284920000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 285820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 286600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 287200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 318495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 319040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 319515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 320040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 321465000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 322095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 322725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 323415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 324105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 325680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 326380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 327780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 328480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 331480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 332180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 332805000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 333400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 334000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 334995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 335580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 337305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 337840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 338295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 338840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 340275000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 340875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 341535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 342225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 342885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 344480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 345180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 346580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 347280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 350980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 351615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 352200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 352800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 353805000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 354400000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 356115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 356660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 357135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 357660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 359085000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 359715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 360345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 361035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 361725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 363300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 364000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 365400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 366100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 369800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 370425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 371020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 371620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 372615000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 373200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374680000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 374880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375860000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 375960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376060000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376420000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376540000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376660000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 376780000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379335000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379680000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 379760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 380040000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 381165000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 382300000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 383020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 383280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 387500000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 387780000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 389320000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 389580000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 391200000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 391480000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 393315000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 393675000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394680000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 394960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 395925000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 396220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 396760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 397020000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 399195000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 399480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400100000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 400860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 401640000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 402520000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 402780000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 403060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 403540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 404380000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 404640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 406000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 407320000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 407580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 408940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 409575000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 409860000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 410400000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 410680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 411340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 414825000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 415180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 415905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 416260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 416895000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 417340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 418300000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 418460000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 418740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 419220000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 419600000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 420180000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 420360000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 420640000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 421120000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 422080000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 422340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 422620000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 423345000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 423640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 424245000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 424575000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 424860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 425355000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 425540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 425820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 426300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 426887000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 427080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 427360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 427840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 428445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 428640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 428920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 429400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 429885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 430080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 430360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 430840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 431325000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 431520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 431800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 432280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 433005000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 433200000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 433480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 433960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 434565000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 434895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 435180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 435675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 435860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 436140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 436695000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 436880000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 437160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 437640000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 439125000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 439320000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 439600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 440080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 440985000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 441180000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 441460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 441940000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 445035000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 445305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 445575000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 446115000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 446415000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 446685000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 447345000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 447615000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 448275000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 448845000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 449265000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 450015000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 450285000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 451155000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 454095000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 454395000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 454845000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 455295000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 464115000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 483160000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 484160000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 488760000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 489660000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 490460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 491600000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 492980000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 493680000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 500860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 501640000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 502420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 503445000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 507240000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 508180000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 509080000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 509860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 510460000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 541785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 542300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 542805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 543300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 544755000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 545385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 546045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 546735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 547395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 548960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 548960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 548960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 548960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 549660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 551060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 551060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 551060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 551060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 551760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 554760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 554760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 554760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 554760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 555460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 556095000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 556680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 557280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 558285000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 558880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 560625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 561140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 561645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 562140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 563595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 564225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 564885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 565575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 566235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 567800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 567800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 567800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 567800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 568500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 569900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 569900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 569900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 569900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 570600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 573600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 573600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 573600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 573600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 574300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 574935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 575520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 576120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 577125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 577720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 579465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 579980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 580485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 580980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 582435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 583065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 583725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 584415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 585075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 586640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 586640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 586640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 586640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 587340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 588740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 588740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 588740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 588740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 589440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 592440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 592440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 592440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 592440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 593140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 593775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 594360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 594960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 595965000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 596560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 597940000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 598040000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 598240000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599120000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599220000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599320000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599420000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599780000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 599900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 600020000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 600140000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 602685000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 603000000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 603080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 603360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 604485000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 605620000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 606340000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 606600000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 610820000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 611100000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 612640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 612900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 614520000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 614800000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 616665000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 617055000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 617560000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 617820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 618100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 618360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 619335000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 619620000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 620160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 620440000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 622665000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 622960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 623500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 623580000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 624340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 625080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 626060000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 626340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 626620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 627100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 627940000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 628200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 629560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 630880000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 631140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 632500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 633135000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 633420000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 633960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 634240000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 634900000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 638415000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 638760000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 639525000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 639880000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 640545000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 640980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 641940000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 642120000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 642400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 642880000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 643260000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 643940000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 644120000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 644400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 644880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 645840000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 646120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 646380000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 647145000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 647440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 648045000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 648375000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 648660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 649155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 649340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 649620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 650100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 650717000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 650900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 651180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 651660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 652275000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 652460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 652740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 653220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 653715000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 653900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 654180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 654660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 655155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 655340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 655620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 656100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 656865000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 657060000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 657340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 657820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 658425000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 658755000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 659040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 659535000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 659720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 660000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 660585000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 660780000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 661060000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 661540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 663015000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 663200000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 663480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 663960000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 664845000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 665040000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 665320000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 665800000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 669045000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 669345000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 669645000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 670215000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 670545000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 670845000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 671535000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 671835000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 672525000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 673155000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 673605000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 674385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 674685000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 675585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 678555000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 678885000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 679365000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 679845000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 688695000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 709200000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 710200000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 714900000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 715800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 716600000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 717840000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 719240000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 719940000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 727220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 727980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 728760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 729795000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 733680000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 734620000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 735520000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 736300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 736900000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 768255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 768840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 769365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 769940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 771435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 772095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 772845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 773535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 774315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 775940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 775940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 775940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 775940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 776640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 778040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 778040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 778040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 778040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 778740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 781840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 781840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 781840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 781840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 782640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 783285000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 783880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 784480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 785475000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 786060000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 787845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 788420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 788955000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 789520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 791025000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 791715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 792465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 793245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 794025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 795620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 795620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 795620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 795620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 796320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 797720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 797720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 797720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 797720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 798420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 801520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 801520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 801520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 801520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 802320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 802965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 803560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 804160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 805155000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 805740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 807525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 808100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 808635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 809200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 810705000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 811395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 812145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 812925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 813705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 815300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 815300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 815300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 815300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 816000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 817400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 817400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 817400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 817400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 818100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 821200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 821200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 821200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 821200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 822000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 822645000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 823240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 823840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 824835000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 825420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 826800000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 826900000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 827100000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 827980000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828080000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828180000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828280000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828760000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 828880000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 829000000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 831555000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 831900000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 831980000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 832260000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 833385000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 834520000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 835240000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 835500000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 839820000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 840100000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 841640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 841920000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 843540000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 843820000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 845715000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 846135000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 846680000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 846960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 847240000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 847500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 848505000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 848800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 849340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 849600000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 851895000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 852180000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 852720000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 852800000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 853560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 854340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 855320000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 855600000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 855880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 856360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 857200000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 857460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 858820000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 860140000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 860400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 861760000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 862395000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 862680000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 863220000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 863500000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 864160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 867705000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 868060000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 868845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 869200000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 869895000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 870340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 871400000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 871580000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 871860000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 872340000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 872720000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 873400000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 873560000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 873840000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 874320000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 875380000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 875640000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 875920000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 876705000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 877000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 877605000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 877935000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 878220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 878715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 878900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 879180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 879660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 880307000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 880500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 880780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 881260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 881865000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 882060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 882340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 882820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 883305000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 883500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 883780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 884260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 884745000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 884940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 885220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 885700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 886485000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 886680000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 886960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 887440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 888045000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 888375000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 888660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 889155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 889340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 889620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 890235000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 890420000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 890700000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 891180000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 892665000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 892860000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 893140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 893620000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 894525000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 894720000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 895000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 895480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 898755000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 899085000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 899415000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 900015000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 900375000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 900705000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 901425000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 901755000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 902475000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 903105000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 903585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 904395000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 904725000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 905655000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 908655000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 909015000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 909525000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 910035000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 918915000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 939460000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 940560000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 945360000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 946260000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 947060000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 948300000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 949700000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 950400000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 957880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 958760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 959620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 960705000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 964700000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 965640000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 966540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 967320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 967920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 970040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 971205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 971500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 972520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 973365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 973660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 974860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 976485000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 976780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 988000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1003425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1003720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1004400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1004680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1005020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1005840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1006120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1006380000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1006660000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1007000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1007355000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1007420000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1008420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1008700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1009040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1010880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1011160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1011420000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1011700000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1012040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1012395000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1012460000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1015160000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1017990000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1020080000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1022910000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1024500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1024780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1024860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1025520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1025800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1025880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1026540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1026820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1026900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1027560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1027840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1027920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1029420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1029700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1029780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1030440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1030720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1030800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1031460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1031740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1031820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1032480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1032760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1032840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1034340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1035100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1035360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1035440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1036080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1036840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1037100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1037180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1037820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1038580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1038840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1038920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1039560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1040320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1040580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1040660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1042140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1042900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1043355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1043420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1044060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1044820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1045275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1045340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1045980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1046740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1047195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1047260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1047900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1048660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1049115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1049180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1049625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1049955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1050285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1050615000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1050945000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1051275000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1051605000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1053300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1054455000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1054740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1055780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1056645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1056940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1058140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1059765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1060060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1071280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1086705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1087000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1087680000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1087960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1088300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1089120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1089400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1089660000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1089940000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1090280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1090635000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1090700000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1091700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1091980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1092320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1094160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1094440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1094700000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1094980000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1095320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1095675000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1095740000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1098440000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1101270000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1103360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1106190000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1107780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1108060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1108140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1108800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1109080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1109160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1109820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1110100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1110180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1110840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1111120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1111200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1112700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1112980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1113060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1113720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1114000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1114080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1114740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1115020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1115100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1115760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1116040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1116120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1117620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1118380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1118640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1118720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1119360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1120120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1120380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1120460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1121100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1121860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1122120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1122200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1122840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1123600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1123860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1123940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1125420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1126180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1126635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1126700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1127340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1128100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1128555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1128620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1129260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1130020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1130475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1130540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1131180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1131940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1132395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1132460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1132905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1133235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1133565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1133895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1134225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1134555000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1134885000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1136580000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1137735000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1138020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1139060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1139925000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1140220000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1141420000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1143045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1143340000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1154560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1169985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1170280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1170960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1171240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1171580000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1172400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1172680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1172940000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1173220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1173560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1173915000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1173980000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1174980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1175260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1175600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1177440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1177720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1177980000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1178260000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1178600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1178955000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1179020000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1181720000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1184550000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1186640000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1189470000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1191060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1191340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1191420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1192080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1192360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1192440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1193100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1193380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1193460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1194120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1194400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1194480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1195980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1196260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1196340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1197000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1197280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1197360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1198020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1198300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1198380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1199040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1199320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1199400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1200900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1201660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1201920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1202000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1202640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1203400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1203660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1203740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1204380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1205140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1205400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1205480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1206120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1206880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1207140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1207220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1208700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1209460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1209915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1209980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1210620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1211380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1211835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1211900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1212540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1213300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1213755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1213820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1214460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1215220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1215675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1215740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1216185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1216515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1216845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1217175000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1217505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1217835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1218165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1219860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1221015000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1221300000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1222340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1223205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1223500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1224700000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1226325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1226620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1237840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1253265000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1253560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1254240000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1254520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1254860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1255680000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1255960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1256220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1256500000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1256840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1257195000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1257260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1258260000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1258540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1258880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1260720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1261000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1261260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1261540000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1261880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1262235000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1262300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1265000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1267830000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1269920000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1272750000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1274340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1274620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1274700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1275360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1275640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1275720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1276380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1276660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1276740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1277400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1277680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1277760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1279260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1279540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1279620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1280280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1280560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1280640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1281300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1281580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1281660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1282320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1282600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1282680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1284180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1284940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1285200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1285280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1285920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1286680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1286940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1287020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1287660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1288420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1288680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1288760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1289400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1290160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1290420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1290500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1291980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1292740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1293195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1293260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1293900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1294660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1295115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1295180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1295820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1296580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1297035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1297100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1297740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1298500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1298955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1299020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1299465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1299795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1300125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1300455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1300785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1301115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1301445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1303425000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1303995000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1304280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1304865000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1305435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1305720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1306305000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1306875000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1307160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1307865000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1308435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1308720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1309755000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1310295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1310580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1311615000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1312155000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1312440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1313985000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1314555000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1314840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1316385000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1316955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1317240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1318215000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1318500000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1320375000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1320915000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1321200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1334020000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1344080000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1365580000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1368180000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1369125000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1380880000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1391540000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1392795000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1393905000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1394415000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1394835000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1395255000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1396155000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1396965000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1397775000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1399365000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1399785000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1400685000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1401495000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1402725000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1402935000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1403145000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1403355000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1403565000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1403775000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1403985000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1404195000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1404405000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1404615000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1404825000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1405035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1405245000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1405725000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1406020000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1410285000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1414185000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1416160000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1422680000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1425870000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1457715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1458240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1458675000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1459200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1460565000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1461165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1461795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1462515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1463205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1464760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1464760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1464760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1464760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1465480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1466800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1466800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1466800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1466800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1467520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1470160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1470160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1470160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1470160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1470880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1471545000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1472140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1472740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1473765000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1474360000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1476075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1476600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1477035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1477560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1478925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1479525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1480155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1480875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1481565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1483120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1483120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1483120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1483120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1483840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1485160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1485160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1485160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1485160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1485880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1488520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1488520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1488520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1488520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1489240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1489905000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1490500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1491100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1492125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1492720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1494435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1494960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1495395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1495920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1497285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1497885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1498515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1499235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1499925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1501480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1501480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1501480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1501480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1502200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1503520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1503520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1503520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1503520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1504240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1506880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1506880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1506880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1506880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1507600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1508265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1508860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1509460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1510485000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1511080000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1512540000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1512660000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1512860000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1513900000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514020000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514120000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514220000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514780000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1514900000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1515020000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1517625000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1517960000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1518040000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1518320000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1519545000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1520780000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1521560000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1521840000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1525860000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1526160000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1527600000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1527900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1529500000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1529780000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1531635000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1531965000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1532480000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1532780000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1533080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1533380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1534395000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1534700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1535300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1535600000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1537695000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1538000000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1538600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1538680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1539480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1540280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1541180000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1541480000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1541780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1542300000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1543060000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1543340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1544600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1545840000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1546140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1547380000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1548045000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1548360000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1548960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1549260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1549940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1553445000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1553820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1554525000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1554900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1555515000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1555980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1556940000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1557120000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1557420000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1557920000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1558320000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1558900000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1559060000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1559360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1559880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1560840000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1561140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1561440000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1562145000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1562460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1563075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1563405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1563720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1564215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1564400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1564700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1565220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1565777000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1565960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1566260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1566780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1567395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1567580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1567880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1568400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1568895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1569080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1569380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1569900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1570395000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1570580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1570880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1571400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1572105000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1572300000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1572600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1573100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1573725000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1574055000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1574360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1574865000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1575060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1575360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1575885000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1576080000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1576380000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1576880000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1578405000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1578600000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1578900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1579400000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1580385000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1580580000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1580880000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1581380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1584675000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1584915000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1585155000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1585695000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1585965000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1586205000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1586835000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1587075000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1587705000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1588305000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1588665000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1589385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1589625000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1590435000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1594575000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1594845000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1595235000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1595625000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1602705000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1622240000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1623200000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1627560000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1628380000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1629100000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1630220000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1631540000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1632260000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1638940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1639720000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1640500000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1641585000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1644860000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1645740000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1646640000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1647420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1648020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1680045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1680540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1681005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1681500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1682895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1683495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1684125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1684845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1685535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1687060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1687060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1687060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1687060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1687780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1689100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1689100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1689100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1689100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1689820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1692460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1692460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1692460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1692460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1693180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1693845000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1694440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1695040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1696065000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1696660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1698405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1698900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1699365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1699860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1701255000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1701855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1702485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1703205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1703895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1705420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1705420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1705420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1705420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1706140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1707460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1707460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1707460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1707460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1708180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1710820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1710820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1710820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1710820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1711540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1712205000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1712800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1713400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1714425000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1715020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1716765000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1717260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1717725000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1718220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1719615000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1720215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1720845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1721565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1722255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1723780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1723780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1723780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1723780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1724500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1725820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1725820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1725820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1725820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1726540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1729180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1729180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1729180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1729180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1729900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1730565000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1731160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1731760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1732785000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1733380000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1734840000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1734960000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1735160000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1736200000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1736320000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1736420000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1736520000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1736940000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1737080000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1737200000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1737320000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1739925000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1740260000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1740340000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1740620000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1741845000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1743080000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1743860000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1744140000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1748280000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1748580000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1750140000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1750440000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1752040000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1752320000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1754205000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1754565000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1755140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1755440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1755740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1756040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1757085000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1757400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1758000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1758300000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1760415000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1760720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1761320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1761400000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1762200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1763000000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1763900000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1764200000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1764500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1765020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1765780000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1766060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1767440000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1768680000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1768980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1770220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1770885000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1771200000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1771800000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1772100000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1772780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1776315000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1776680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1777425000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1777800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1778445000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1778900000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1779900000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1780080000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1780380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1780880000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1781280000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1781980000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1782140000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1782440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1782960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1783920000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1784220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1784520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1785255000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1785560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1786185000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1786515000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1786820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1787325000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1787520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1787820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1788320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1788917000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1789100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1789400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1789920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1790535000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1790720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1791020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1791540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1792035000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1792220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1792520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1793040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1793535000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1793720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1794020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1794540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1795275000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1795460000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1795760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1796280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1796895000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1797225000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1797540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1798035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1798220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1798520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1799085000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1799280000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1799580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1800080000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1801605000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1801800000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1802100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1802600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1803585000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1803780000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1804080000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1804580000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1807905000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1808175000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1808445000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1809015000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1809315000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1809585000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1810245000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1810515000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1811175000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1811805000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1812195000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1812945000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1813215000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1814055000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1818225000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1818525000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1818945000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1819365000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1826475000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1845980000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1846940000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1851420000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1852240000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1852960000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1854080000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1855520000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1856240000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1862920000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1863700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1864480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1865595000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1868980000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1869860000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1870780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1871580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1872180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1904235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1904820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1905315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1905900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1907325000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1907985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1908735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1909455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1910145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1911760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1911760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1911760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1911760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1912480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1913920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1913920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1913920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1913920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1914640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1917400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1917400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1917400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1917400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1918240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1918905000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1919500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1920100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1921125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1921720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1923495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1924080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1924575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1925160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1926585000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1927245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1927995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1928715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1929405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1931020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1931020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1931020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1931020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1931740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1933180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1933180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1933180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1933180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1933900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1936660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1936660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1936660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1936660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1937500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1938165000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1938760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1939360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1940385000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1940980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1942755000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1943340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1943835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1944420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1945845000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1946505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1947255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1947975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1948665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1950280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1950280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1950280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1950280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1951000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1952440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1952440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1952440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1952440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1953160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1955920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1955920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1955920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1955920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1956760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1957425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1958020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1958620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1959645000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1960240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1961700000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1961820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1962020000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963060000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963180000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963280000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963380000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963800000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1963940000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1964060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1964180000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1966935000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967300000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1967660000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1968885000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1970120000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1970900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1971180000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1975460000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1975760000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1977320000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1977620000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1979240000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1979540000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1981455000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1981845000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982360000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1982960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1983260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1984335000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1984640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1985240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1985540000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1987755000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1988740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1989540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1990340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991360000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991660000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1991960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1992480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1993360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1993640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1995020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1996260000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1996560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1997920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1998585000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1998900000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1999500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 1999800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2000480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2004195000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2004560000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2005335000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2005700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2006385000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2006840000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2007960000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2008140000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2008440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2008940000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2009340000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2010040000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2010200000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2010500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2011020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2012100000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2012400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2012700000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2013465000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2013780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2014395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2014725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2015040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2015535000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2015720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2016020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2016540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2017157000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2017340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2017640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2018160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2018775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2018960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2019260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2019780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2020275000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2020460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2020760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2021280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2021775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2021960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2022260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2022780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2023545000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2023740000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2024040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2024540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2025165000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2025495000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2025800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2026305000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2026500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2026800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2027385000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2027580000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2027880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2028380000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2029905000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2030100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2030400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2030900000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2031885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2032080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2032380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2032880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2036235000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2036535000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2036835000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2037435000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2037765000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2038065000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2038755000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2039055000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2039745000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2040405000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2040825000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2041605000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2041905000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2042775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2046975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2047305000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2047755000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2048205000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2055345000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2074940000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2076020000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2080600000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2081520000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2082360000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2083480000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2084920000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2085640000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2092420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2093320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2094220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2095365000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2098880000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2099760000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2100660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2101440000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2102040000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2134965000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2135520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2136045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2136600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2138055000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2138715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2139465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2140185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2140875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2142460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2142460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2142460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2142460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2143180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2144620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2144620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2144620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2144620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2145340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2148100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2148100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2148100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2148100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2148940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2149605000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2150200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2150800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2151825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2152420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2154225000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2154780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2155305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2155860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2157315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2157975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2158725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2159445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2160135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2161720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2161720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2161720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2161720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2162440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2164600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2167360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2167360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2167360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2167360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2168200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2168865000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2169460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2170060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2171085000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2171680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2173485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2174040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2174565000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2175120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2176575000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2177235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2177985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2178705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2179395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2180980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2180980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2180980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2180980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2181700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2183140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2183140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2183140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2183140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2183860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2186620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2186620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2186620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2186620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2187460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2188125000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2188720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2189320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2190345000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2190940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2192400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2192520000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2192720000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2193760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2193880000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2193980000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2194080000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2194500000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2194640000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2194760000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2194880000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2197635000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2198000000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2198080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2198360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2199585000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2200820000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2201600000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2201880000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2206420000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2206700000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2208400000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2208680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2210440000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2210720000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2212785000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2213205000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2213780000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2214080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2214380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2214680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2215785000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2216100000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2216700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2217000000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2219235000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2219540000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2220140000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2220220000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2221020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2221820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2222840000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2223140000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2223440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2223960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2224840000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2225120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2226500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2227860000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2228160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2229520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2230185000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2230500000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2231100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2231400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2232080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2235945000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2236320000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2237115000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2237480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2238195000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2238660000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2239740000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2239920000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2240220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2240720000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2241120000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2241820000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2241980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2242280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2242800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2243880000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2244180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2244480000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2245275000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2245580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2246205000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2246535000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2246840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2247345000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2247540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2247840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2248340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2248997000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2249180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2249480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2250000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2250615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2250800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2251100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2251620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2252115000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2252300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2252600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2253120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2253615000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2253800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2254100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2254620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2255415000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2255600000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2255900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2256420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2257035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2257365000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2257680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2258175000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2258360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2258660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2259285000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2259480000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2259780000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2260280000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2261805000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2262000000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2262300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2262800000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2263785000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2263980000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2264280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2264780000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2268165000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2268495000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2268825000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2269455000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2269815000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2270145000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2270865000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2271195000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2271915000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2272605000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2273055000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2273865000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2274195000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2275095000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2279325000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2279685000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2280165000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2280645000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2287815000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2307380000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2308460000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2313160000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2314080000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2314920000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2316040000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2317480000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2318200000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2325220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2326120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2327020000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2328195000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2331700000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2332700000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2333620000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2334420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2335020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2337320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2338635000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2338940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2340100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2341125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2341440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2342760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2344665000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2344980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2358100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2375805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2376120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2376860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2377160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2377540000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2378420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2378720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2379020000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2379320000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2379700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2380095000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2380160000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2381280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2381580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2381960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2384000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2384300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2384600000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2384900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2385280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2385675000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2385740000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2388780000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2391780000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2394200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2397210000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2398940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2399240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2399320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2400020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2400320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2400400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2401100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2401400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2401480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2402180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2402480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2402560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2404160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2404460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2404540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2405240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2405540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2405620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2406320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2406620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2406700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2407400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2407700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2407780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2409380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2410200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2410500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2410580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2411300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2412120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2412420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2412500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2413220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2414040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2414340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2414420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2415140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2415960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2416260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2416340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2417960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2418780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2419275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2419340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2420060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2420880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2421375000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2421440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2422160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2422980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2423475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2423540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2424260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2425080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2425575000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2425640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2426085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2426415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2426745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2427075000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2427405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2427735000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2428065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2429840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2431155000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2431460000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2432620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2433645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2433960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2435280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2437185000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2437500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2450620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2468325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2468640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2469380000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2469680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2470060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2470940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2471240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2471540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2471840000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2472220000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2472615000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2472680000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2473800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2474100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2474480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2476520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2476820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2477120000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2477420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2477800000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2478195000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2478260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2481300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2484300000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2486720000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2489730000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2491460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2491760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2491840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2492540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2492840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2492920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2493620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2493920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2494000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2494700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2495000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2495080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2496680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2496980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2497060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2497760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2498060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2498140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2498840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2499140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2499220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2499920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2500220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2500300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2501900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2502720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2503020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2503100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2503820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2504640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2504940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2505020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2505740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2506560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2506860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2506940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2507660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2508480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2508780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2508860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2510480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2511300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2511795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2511860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2512580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2513400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2513895000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2513960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2514680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2515500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2515995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2516060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2516780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2517600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2518095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2518160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2518605000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2518935000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2519265000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2519595000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2519925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2520255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2520585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2522360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2523675000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2523980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2525140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2526165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2526480000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2527800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2529705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2530020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2543140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2560845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2561160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2561900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2562200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2562580000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2563460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2563760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2564060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2564360000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2564740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2565135000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2565200000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2566320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2566620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2567000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2569040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2569340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2569640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2569940000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2570320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2570715000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2570780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2573820000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2576820000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2579240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2582250000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2583980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2584280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2584360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2585060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2585360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2585440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2586140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2586440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2586520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2587220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2587520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2587600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2589200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2589500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2589580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2590280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2590580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2590660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2591360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2591660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2591740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2592440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2592740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2592820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2594420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2595240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2595540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2595620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2596340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2597160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2597460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2597540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2598260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2599080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2599380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2599460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2600180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2601000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2601300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2601380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2603000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2603820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2604315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2604380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2605100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2605920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2606415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2606480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2607200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2608020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2608515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2608580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2609300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2610120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2610615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2610680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2611125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2611455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2611785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2612115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2612445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2612775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2613105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2614880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2616195000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2616500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2617660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2618685000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2619000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2620320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2622225000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2622540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2635660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2653365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2653680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2654420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2654720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2655100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2655980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2656280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2656580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2656880000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2657260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2657655000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2657720000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2658840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2659140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2659520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2661560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2661860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2662160000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2662460000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2662840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2663235000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2663300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2666340000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2669340000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2671760000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2674770000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2676500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2676800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2676880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2677580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2677880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2677960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2678660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2678960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2679040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2679740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2680040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2680120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2681720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2682020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2682100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2682800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2683100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2683180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2683880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2684180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2684260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2684960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2685260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2685340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2686940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2687760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2688060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2688140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2688860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2689680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2689980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2690060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2690780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2691600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2691900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2691980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2692700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2693520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2693820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2693900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2695520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2696340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2696835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2696900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2697620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2698440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2698935000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2699000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2699720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2700540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2701035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2701100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2701820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2702640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2703135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2703200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2703645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2703975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2704305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2704635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2704965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2705295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2705625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2707695000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2708265000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2708580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2709225000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2709825000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2710140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2710785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2711385000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2711700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2712525000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2713125000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2713440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2714655000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2715225000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2715540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2716755000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2717325000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2717640000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2719455000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2720025000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2720340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2722155000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2722725000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2723040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2724195000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2724500000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2726475000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2727045000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2727360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2742100000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2754040000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2779540000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2782280000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2783295000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2796940000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2809480000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2810865000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2812125000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2812620000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2812995000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2813385000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2814315000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2815155000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2815995000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2817560000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2817945000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2818875000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2819715000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2820945000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2821155000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2821365000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2821575000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2821785000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2821995000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2822205000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2822415000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2822625000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2822835000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2823045000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2823255000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2823465000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2823975000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2824280000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2828595000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2832525000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2834620000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2841140000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2844450000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2878335000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2878880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2879325000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2879860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2881155000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2881785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2882475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2883165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2883855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2885440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2885440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2885440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2885440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2886140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2887540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2887540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2887540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2887540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2888240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2890620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2890620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2890620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2890620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2891320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2891985000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2892680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2893240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2894325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2895020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2896935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2897480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2897925000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2898460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2899755000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2900385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2901075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2901765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2902455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2904040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2904040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2904040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2904040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2904740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2906140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2906140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2906140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2906140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2906840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2909220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2909220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2909220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2909220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2909920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2910585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2911280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2911840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2912925000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2913620000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2915535000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2916080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2916525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2917060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2918355000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2918985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2919675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2920365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2921055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2922640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2922640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2922640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2922640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2923340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2924740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2924740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2924740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2924740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2925440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2927820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2927820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2927820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2927820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2928520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2929185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2929880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2930440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2931525000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2932220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2933920000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2934060000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2934260000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2935460000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2935600000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2935700000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2935800000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2936280000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2936440000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2936560000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2936680000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2939565000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2939920000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2940000000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2940320000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2941635000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2942920000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2943740000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2944040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2948420000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2948740000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2950400000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2950720000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2952540000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2952860000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2954895000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2955225000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2955800000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2956120000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2956420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2956720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2957775000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2958100000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2958700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2959000000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2961105000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2961440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2962060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2962140000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2963020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2963860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2964860000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2965180000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2965480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2966020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2966760000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2967080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2968400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2969580000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2969900000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2971220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2971905000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2972240000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2972860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2973160000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2973920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2977845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2978240000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2978985000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2979380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2980035000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2980520000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2981660000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2981840000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2982160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2982700000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2983100000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2983780000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2983940000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2984260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2984800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2985920000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2986240000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2986540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2987295000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2987620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2988255000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2988585000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2988920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2989455000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2989640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2989960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2990500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2991077000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2991260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2991580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2992120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2992755000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2992940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2993260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2993800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2994315000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2994500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2994820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2995360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2995875000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2996060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2996380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2996920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2997675000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2997860000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2998180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2998720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2999355000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 2999685000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3000020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3000555000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3000740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3001060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3001605000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3001800000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3002120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3002680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3004335000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3004520000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3004840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3005380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3006285000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3006480000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3006800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3007360000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3010845000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3011085000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3011325000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3011895000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3012165000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3012405000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3013035000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3013275000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3013875000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3014505000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3014835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3015555000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3015795000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3016575000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3021975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3022245000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3022605000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3022965000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3028335000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3047220000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3048200000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3052480000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3053320000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3054020000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3055040000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3056440000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3057140000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3063280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3064140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3065020000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3066165000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3069040000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3069920000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3070860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3071680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3072280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3106305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3106820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3107295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3107800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3109125000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3109755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3110475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3111165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3111825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3113420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3113420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3113420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3113420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3114120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3115520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3115520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3115520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3115520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3116220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3118600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3118600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3118600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3118600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3119440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3120105000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3120800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3121360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3122445000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3123140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3125085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3125600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3126075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3126580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3127905000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3128535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3129255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3129945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3130605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3132200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3132200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3132200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3132200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3132900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3134300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3134300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3134300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3134300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3135000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3137380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3137380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3137380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3137380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3138220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3138885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3139580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3140140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3141225000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3141920000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3143865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3144380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3144855000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3145360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3146685000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3147315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3148035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3148725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3149385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3150980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3150980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3150980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3150980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3151680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3153080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3153080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3153080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3153080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3153780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3156160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3156160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3156160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3156160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3157000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3157665000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3158360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3158920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3160005000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3160700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3162400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3162540000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3162740000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3163940000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3164080000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3164180000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3164280000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3164760000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3164920000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3165040000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3165160000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3168045000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3168400000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3168480000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3168800000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3170115000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3171400000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3172220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3172520000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3176900000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3177220000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3178880000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3179200000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3181020000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3181340000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3183405000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3183765000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3184280000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3184600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3184900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3185200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3186285000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3186620000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3187240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3187540000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3189705000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3190040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3190660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3190740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3191620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3192460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3193460000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3193780000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3194080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3194620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3195500000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3195820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3197120000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3198300000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3198620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3199940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3200625000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3200960000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3201580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3201880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3202640000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3206595000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3206980000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3207735000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3208120000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3208785000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3209260000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3210380000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3210560000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3210880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3211420000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3211820000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3212500000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3212660000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3212980000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3213520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3214640000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3214960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3215260000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3216045000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3216380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3217035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3217365000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3217700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3218235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3218420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3218740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3219280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3219887000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3220080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3220400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3220960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3221595000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3221780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3222100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3222640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3223155000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3223340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3223660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3224200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3224715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3224900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3225220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3225760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3226545000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3226740000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3227060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3227620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3228255000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3228585000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3228920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3229455000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3229640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3229960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3230535000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3230720000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3231040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3231580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3233235000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3233420000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3233740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3234280000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3235185000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3235380000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3235700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3236260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3239775000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3240045000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3240315000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3240885000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3241185000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3241455000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3242085000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3242355000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3242985000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3243645000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3244005000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3244755000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3245025000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3245835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3251265000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3251565000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3251955000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3252345000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3257745000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3276620000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3277600000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3281880000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3282720000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3283420000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3284440000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3285820000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3286520000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3292740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3293620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3294480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3295665000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3298680000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3299560000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3300480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3301300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3301900000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3335955000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3336580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3337065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3337700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3339075000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3339765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3340455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3341145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3341835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3343360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3343360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3343360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3343360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3344060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3345460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3345460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3345460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3345460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3346160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3348540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3348540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3348540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3348540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3349380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3350055000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3350600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3351160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3352245000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3352940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3354915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3355540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3356025000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3356660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3358035000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3358725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3359415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3360105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3360795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3362320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3362320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3362320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3362320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3363020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3364420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3364420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3364420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3364420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3365120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3367500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3367500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3367500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3367500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3368340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3369015000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3369560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3370120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3371205000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3371900000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3373875000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3374500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3374985000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3375620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3376995000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3377685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3378375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3379065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3379755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3381280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3381280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3381280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3381280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3381980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3383380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3383380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3383380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3383380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3384080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3386460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3386460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3386460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3386460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3387300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3387975000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3388520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3389080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3390165000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3390860000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3392560000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3392700000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3392900000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3394100000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3394240000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3394340000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3394440000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3394920000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3395080000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3395200000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3395320000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3398205000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3398560000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3398640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3398960000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3400275000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3401560000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3402380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3402680000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3407060000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3407380000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3409040000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3409360000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3411180000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3411500000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3413595000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3413985000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3414580000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3414880000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3415180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3415480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3416595000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3416920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3417520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3417820000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3420045000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3420380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3421000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3421080000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3421960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3422800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3423800000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3424120000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3424420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3424960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3425840000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3426160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3427460000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3428780000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3429100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3430400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3431085000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3431420000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3432040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3432340000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3433100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3437085000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3437480000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3438285000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3438680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3439395000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3439880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3441020000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3441200000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3441520000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3442060000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3442460000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3443140000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3443300000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3443620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3444160000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3445280000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3445600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3445900000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3446715000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3447040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3447675000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3448005000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3448340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3448875000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3449060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3449380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3449920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3450557000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3450740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3451060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3451600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3452235000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3452420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3452740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3453280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3453795000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3453980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3454300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3454840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3455355000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3455540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3455860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3456400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3457215000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3457400000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3457720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3458260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3458895000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3459225000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3459560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3460095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3460280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3460600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3461205000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3461400000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3461720000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3462280000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3463935000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3464120000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3464440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3464980000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3465885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3466080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3466400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3466960000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3470505000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3470805000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3471105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3471735000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3472065000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3472365000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3473055000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3473355000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3474015000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3474705000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3475095000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3475875000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3476175000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3477015000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3482475000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3482805000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3483225000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3483645000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3489075000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3507940000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3509060000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3513580000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3514420000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3515260000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3516280000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3517660000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3518360000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3524740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3525600000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3526480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3527685000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3530700000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3531580000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3532500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3533320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3533920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3568005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3568600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3569115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3569720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3571125000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3571815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3572535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3573345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3574035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3575680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3575680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3575680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3575680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3576520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3577900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3577900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3577900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3577900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3578740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3581100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3581100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3581100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3581100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3581940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3582615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3583160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3583720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3584805000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3585500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3587505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3588100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3588615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3589220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3590625000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3591315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3592035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3592845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3593535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3595180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3595180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3595180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3595180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3596020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3597400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3597400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3597400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3597400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3598240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3600600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3600600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3600600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3600600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3601440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3602115000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3602660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3603220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3604305000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3605000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3607005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3607600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3608115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3608720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3610125000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3610815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3611535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3612345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3613035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3614680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3614680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3614680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3614680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3615520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3616900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3616900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3616900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3616900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3617740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3620100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3620100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3620100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3620100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3620940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3621615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3622160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3622720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3623805000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3624500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3626200000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3626340000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3626540000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3627740000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3627880000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3627980000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3628080000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3628560000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3628720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3628840000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3628960000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3631845000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3632200000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3632280000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3632600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3633915000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3635200000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3636020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3636320000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3640840000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3641140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3642800000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3643120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3644940000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3645260000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3647385000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3647805000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3648480000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3648800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3649120000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3649420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3650565000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3650900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3651520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3651820000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3654105000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3654440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3655060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3655140000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3656020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3656860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3657860000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3658180000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3658480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3659020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3659900000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3660220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3661520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3662840000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3663160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3664460000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3665145000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3665480000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3666100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3666400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3667160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3671175000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3671560000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3672375000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3672760000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3673485000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3673960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3675080000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3675260000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3675580000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3676120000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3676520000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3677200000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3677360000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3677680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3678220000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3679340000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3679660000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3679960000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3680805000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3681140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3681795000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3682125000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3682460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3682995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3683180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3683500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3684040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3684707000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3684900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3685220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3685780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3686415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3686600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3686920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3687460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3687975000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3688160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3688480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3689020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3689535000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3689720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3690040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3690580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3691425000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3691620000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3691940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3692500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3693135000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3693465000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3693800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3694335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3694520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3694840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3695475000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3695660000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3695980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3696520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3698175000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3698360000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3698680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3699220000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3700125000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3700320000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3700640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3701200000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3704775000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3705105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3705435000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3706065000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3706425000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3706755000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3707445000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3707775000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3708465000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3709185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3709605000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3710415000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3710745000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3711615000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3717105000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3717465000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3717915000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3718365000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3723825000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3742820000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3743940000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3748460000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3749400000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3750240000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3751260000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3752660000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3753500000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3759880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3760740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3761620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3762855000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3766000000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3767020000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3767940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3768760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3769360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3771860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3772845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3773180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3774260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3775065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3775400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3776580000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3777855000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3778180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3785840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3798165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3798500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3799260000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3799580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3799980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3800780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3801100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3801400000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3801700000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3802080000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3802485000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3802560000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3803500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3803800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3804180000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3805640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3805960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3806260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3806560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3806940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3807345000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3807420000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3810320000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3813150000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3815300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3818130000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3819880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3820180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3820260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3820960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3821260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3821340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3822040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3822340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3822420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3823120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3823420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3823500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3825160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3825460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3825540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3826240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3826540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3826620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3827320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3827620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3827700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3828400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3828700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3828780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3830440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3831280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3831580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3831660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3832360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3833200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3833500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3833580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3834280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3835120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3835420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3835500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3836200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3837040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3837340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3837420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3839080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3839920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3840435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3840500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3841180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3842020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3842535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3842600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3843280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3844120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3844635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3844700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3845380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3846220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3846735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3846800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3847245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3847575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3847905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3848235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3848565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3848895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3849225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3851120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3852105000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3852440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3853520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3854325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3854660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3855840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3857115000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3857440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3865100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3877425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3877760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3878520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3878840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3879240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3880040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3880360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3880660000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3880960000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3881340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3881745000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3881820000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3882760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3883060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3883440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3884900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3885220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3885520000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3885820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3886200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3886605000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3886680000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3889580000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3892410000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3894560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3897390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3899140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3899440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3899520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3900220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3900520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3900600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3901300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3901600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3901680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3902380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3902680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3902760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3904420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3904720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3904800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3905500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3905800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3905880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3906580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3906880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3906960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3907660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3907960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3908040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3909700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3910540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3910840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3910920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3911620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3912460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3912760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3912840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3913540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3914380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3914680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3914760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3915460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3916300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3916600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3916680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3918340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3919180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3919695000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3919760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3920440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3921280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3921795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3921860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3922540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3923380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3923895000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3923960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3924640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3925480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3925995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3926060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3926505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3926835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3927165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3927495000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3927825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3928155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3928485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3930380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3931365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3931700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3932780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3933585000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3933920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3935100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3936375000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3936700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3944360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3956685000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3957020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3957780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3958100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3958500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3959300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3959620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3959920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3960220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3960600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3961005000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3961080000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3962020000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3962320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3962700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3964160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3964480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3964780000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3965080000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3965460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3965865000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3965940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3968840000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3971670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3973820000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3976650000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3978400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3978700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3978780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3979480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3979780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3979860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3980560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3980860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3980940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3981640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3981940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3982020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3983680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3983980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3984060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3984760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3985060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3985140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3985840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3986140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3986220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3986920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3987220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3987300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3988960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3989800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3990100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3990180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3990880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3991720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3992020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3992100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3992800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3993640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3993940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3994020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3994720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3995560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3995860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3995940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3997600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3998440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3998955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3999020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 3999700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4000540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4001055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4001120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4001800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4002640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4003155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4003220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4003900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4004740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4005255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4005320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4005765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4006095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4006425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4006755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4007085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4007415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4007745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4009640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4010625000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4010960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4012040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4012845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4013180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4014360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4015635000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4015960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4023620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4035945000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4036280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4037040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4037360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4037760000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4038560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4038880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4039180000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4039480000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4039860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4040265000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4040340000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4041280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4041580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4041960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4043420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4043740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4044040000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4044340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4044720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4045125000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4045200000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4048100000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4050930000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4053080000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4055910000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4057660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4057960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4058040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4058740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4059040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4059120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4059820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4060120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4060200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4060900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4061200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4061280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4062940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4063240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4063320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4064020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4064320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4064400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4065100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4065400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4065480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4066180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4066480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4066560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4068220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4069060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4069360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4069440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4070140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4070980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4071280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4071360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4072060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4072900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4073200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4073280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4073980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4074820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4075120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4075200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4076860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4077700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4078215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4078280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4078960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4079800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4080315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4080380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4081060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4081900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4082415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4082480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4083160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4084000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4084515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4084580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4085025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4085355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4085685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4086015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4086345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4086675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4087005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4089195000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4089795000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4090120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4090695000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4091295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4091620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4092195000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4092795000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4093120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4093785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4094415000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4094740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4095645000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4096275000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4096600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4097505000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4098135000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4098460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4099695000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4100295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4100620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4101855000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4102455000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4102780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4103625000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4103960000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4106055000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4106655000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4106980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4116500000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4123160000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4137340000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4140320000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4141275000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4149560000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4156580000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4157655000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4158585000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4159035000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4159395000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4159755000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4160595000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4161345000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4162095000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4163805000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4164165000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4165005000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4165755000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4167135000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4167345000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4167555000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4167765000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4167975000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4168185000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4168395000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4168605000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4168815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4169025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4169235000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4169445000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4169655000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4170195000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4170520000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4175145000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4178805000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4180500000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4187000000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4190190000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4224555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4225080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4225515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4226040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4227285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4227945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4228575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4229175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4229805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4231220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4231220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4231220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4231220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4232020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4233300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4233300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4233300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4233300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4234100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4236000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4236000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4236000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4236000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4236800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4237485000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4238120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4238760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4239945000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4240580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4242675000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4243200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4243635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4244160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4245405000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4246065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4246695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4247295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4247925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4249340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4249340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4249340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4249340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4250140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4251420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4251420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4251420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4251420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4252220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4254120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4254120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4254120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4254120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4254920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4255605000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4256240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4256880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4258065000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4258700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4260795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4261320000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4261755000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4262280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4263525000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4264185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4264815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4265415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4266045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4267460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4267460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4267460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4267460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4268260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4269540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4269540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4269540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4269540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4270340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4272240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4272240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4272240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4272240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4273040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4273725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4274360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4275000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4276185000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4276820000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4278720000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4278880000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4279080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4280440000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4280600000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4280700000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4280800000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4281340000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4281520000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4281640000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4281760000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4284795000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4285200000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4285280000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4285620000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4287045000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4288420000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4289320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4289640000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4293780000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4294120000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4295660000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4296000000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4297720000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4298040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4300095000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4300425000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4301020000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4301340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4301680000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4302000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4303155000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4303500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4304160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4304500000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4306635000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4306980000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4307640000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4307720000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4308660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4309620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4310600000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4310940000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4311280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4311880000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4312720000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4313040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4314220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4315420000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4315740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4316920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4317615000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4317960000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4318620000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4318960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4319800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4323795000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4324200000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4324965000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4325380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4326045000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4326540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4327660000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4327820000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4328160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4328760000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4329200000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4329820000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4329980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4330320000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4330920000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4332040000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4332360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4332700000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4333515000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4333860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4334535000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4334865000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4335220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4335765000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4335960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4336300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4336900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4337507000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4337700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4338040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4338640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4339305000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4339500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4339840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4340440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4340985000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4341180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4341520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4342120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4342665000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4342860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4343200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4343800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4344615000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4344800000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4345140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4345740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4346415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4346745000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4347100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4347645000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4347840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4348180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4348755000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4348940000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4349280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4349880000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4351725000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4351920000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4352260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4352860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4353885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4354080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4354420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4355020000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4358925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4359165000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4359405000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4359975000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4360245000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4360485000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4361085000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4361325000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4361925000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4362615000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4362915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4363635000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4363875000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4364625000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4371255000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4371525000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4371855000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4372185000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4375845000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4392760000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4393720000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4397840000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4398700000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4399500000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4400500000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4401780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4402580000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4408180000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4409000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4409800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4411065000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4413580000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4414420000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4415380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4416220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4416820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4451355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4452020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4452495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4453140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4454415000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4455075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4455705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4456335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4457115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4458840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4458840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4458840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4458840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4459640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4461060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4461060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4461060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4461060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4461860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4463920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4463920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4463920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4463920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4464720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4465425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4466060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4466700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4467885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4468520000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4470645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4471300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4471755000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4472420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4473705000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4474395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4475175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4475955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4476735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4478460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4478460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4478460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4478460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4479260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4480680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4480680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4480680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4480680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4481480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4483540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4483540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4483540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4483540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4484340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4485045000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4485680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4486320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4487505000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4488140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4490265000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4490920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4491375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4492040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4493325000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4494015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4494795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4495575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4496355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4498080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4498080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4498080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4498080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4498880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4500300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4500300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4500300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4500300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4501100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4503160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4503160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4503160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4503160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4503960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4504665000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4505300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4505940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4507125000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4507760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4509660000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4509820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4510020000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4511380000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4511540000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4511640000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4511740000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4512280000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4512460000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4512580000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4512700000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4515735000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4516140000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4516220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4516560000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4517985000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4519360000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4520260000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4520580000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4524720000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4525060000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4526760000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4527100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4528820000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4529160000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4531245000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4531605000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4532140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4532460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4532800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4533120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4534305000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4534660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4535320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4535640000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4537845000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4538200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4538860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4538940000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4539880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4540800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4541940000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4542280000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4542600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4543200000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4544040000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4544380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4545720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4546920000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4547260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4548600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4549305000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4549660000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4550320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4550640000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4551480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4555515000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4555920000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4556715000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4557120000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4557825000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4558320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4559440000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4559600000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4559940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4560540000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4560980000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4561600000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4561760000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4562100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4562700000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4563820000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4564140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4564480000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4565325000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4565680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4566345000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4566675000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4567020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4567575000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4567760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4568100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4568700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4569347000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4569540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4569880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4570480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4571145000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4571340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4571680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4572280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4572825000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4573020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4573360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4573960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4574505000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4574700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4575040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4575640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4576485000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4576680000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4577020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4577620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4578285000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4578615000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4578960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4579515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4579700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4580040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4580655000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4580840000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4581180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4581780000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4583625000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4583820000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4584160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4584760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4585785000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4585980000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4586320000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4586920000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4590855000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4591125000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4591395000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4591995000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4592295000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4592565000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4593195000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4593465000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4594095000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4594785000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4595115000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4595865000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4596135000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4596915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4603575000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4603875000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4604235000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4604595000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4608285000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4627760000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4628880000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4633160000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4634020000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4634820000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4635820000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4637260000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4638060000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4643940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4644760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4645740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4647015000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4649520000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4650360000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4651320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4652160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4652760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4688415000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4689040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4689525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4690160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4691475000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4692165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4692975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4693755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4694535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4696200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4696200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4696200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4696200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4697000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4698420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4698420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4698420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4698420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4699220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4701280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4701280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4701280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4701280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4702080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4702785000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4703420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4704060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4705245000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4705880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4708035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4708660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4709145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4709780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4711095000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4711785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4712595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4713375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4714155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4715820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4715820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4715820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4715820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4716620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4718040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4718040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4718040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4718040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4718840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4720900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4720900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4720900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4720900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4721700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4722405000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4723040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4723680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4724865000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4725500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4727655000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4728280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4728765000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4729400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4730715000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4731405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4732215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4732995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4733775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4735440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4735440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4735440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4735440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4736240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4737660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4737660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4737660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4737660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4738460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4740520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4740520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4740520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4740520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4741320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4742025000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4742660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4743300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4744485000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4745120000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4747020000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4747180000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4747380000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4748740000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4748900000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4749000000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4749100000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4749640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4749820000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4749940000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4750060000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4753275000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4753680000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4753760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4754100000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4755525000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4756900000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4757800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4758120000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4762620000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4762960000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4764840000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4765180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4767080000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4767420000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4769715000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4770105000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4770740000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4771080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4771420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4771740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4772955000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4773300000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4773960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4774300000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4776555000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4776900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4777560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4777640000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4778580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4779540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4780680000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4781020000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4781340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4781940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4782780000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4783120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4784460000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4785660000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4786000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4787340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4788045000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4788400000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4789060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4789380000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4790220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4794645000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4795060000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4795875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4796280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4797015000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4797520000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4798800000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4798980000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4799320000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4799920000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4800360000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4801140000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4801320000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4801660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4802260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4803540000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4803880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4804200000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4805085000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4805440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4806105000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4806435000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4806780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4807335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4807520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4807860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4808460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4809137000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4809320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4809660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4810260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4810935000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4811120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4811460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4812060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4812615000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4812800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4813140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4813740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4814295000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4814480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4814820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4815420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4816305000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4816500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4816840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4817440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4818105000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4818435000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4818780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4819335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4819520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4819860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4820505000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4820700000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4821040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4821640000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4823475000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4823660000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4824000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4824600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4825605000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4825800000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4826140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4826740000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4830705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4831005000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4831305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4831935000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4832265000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4832565000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4833225000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4833525000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4834185000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4834935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4835295000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4836075000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4836375000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4837185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4843875000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4844205000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4844595000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4844985000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4848705000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4868200000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4869320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4873600000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4874460000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4875260000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4876260000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4877700000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4878500000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4884360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4885340000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4886300000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4887585000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4890260000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4891260000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4892220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4893060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4893660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4929345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4929940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4930455000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4931060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4932405000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4933155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4933935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4934715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4935495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4937160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4937160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4937160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4937160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4937960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4939380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4939380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4939380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4939380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4940180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4942240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4942240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4942240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4942240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4943040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4943745000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4944380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4945020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4946205000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4946840000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4949025000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4949620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4950135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4950740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4952085000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4952835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4953615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4954395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4955175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4956840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4956840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4956840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4956840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4957640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4959060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4959060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4959060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4959060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4959860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4961920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4961920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4961920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4961920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4962720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4963425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4964060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4964700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4965885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4966520000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4968705000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4969300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4969815000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4970420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4971765000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4972515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4973295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4974075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4974855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4976520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4976520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4976520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4976520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4977320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4978740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4978740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4978740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4978740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4979540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4981600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4981600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4981600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4981600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4982400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4983105000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4983740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4984380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4985565000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4986200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4988100000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4988260000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4988460000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4989820000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4989980000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4990080000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4990180000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4990720000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4990900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4991020000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4991140000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4994355000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4994760000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4994840000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4995180000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4996605000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4997980000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4998880000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 4999200000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5003860000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5004180000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5006060000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5006400000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5008300000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5008620000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5010945000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5011365000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5012100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5012440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5012760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5013100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5014365000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5014720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5015380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5015700000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5018025000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5018380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5019040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5019120000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5020060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5020980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5022120000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5022460000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5022780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5023380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5024220000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5024560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5025900000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5027100000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5027440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5028780000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5029485000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5029840000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5030500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5030820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5031660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5036115000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5036520000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5037375000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5037780000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5038545000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5039040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5040320000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5040500000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5040840000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5041440000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5041880000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5042660000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5042840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5043180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5043780000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5045060000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5045400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5045740000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5046645000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5047000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5047665000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5047995000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5048340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5048895000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5049080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5049420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5050020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5050727000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5050920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5051260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5051860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5052525000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5052720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5053060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5053660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5054205000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5054400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5054740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5055340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5055885000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5056080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5056420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5057020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5057925000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5058120000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5058460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5059060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5059725000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5060055000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5060400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5060955000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5061140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5061480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5062155000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5062340000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5062680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5063280000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5065125000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5065320000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5065660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5066260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5067285000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5067480000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5067820000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5068420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5072415000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5072745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5073075000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5073735000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5074095000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5074425000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5075115000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5075445000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5076135000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5076885000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5077275000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5078085000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5078415000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5079255000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5085975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5086335000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5086755000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5087175000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5090925000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5110420000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5111700000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5116240000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5117100000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5117900000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5118900000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5120340000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5121140000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5127140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5128100000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5129060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5130375000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5133200000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5134200000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5135160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5136000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5136600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5139440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5140575000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5140920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5142160000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5143125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5143480000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5144860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5146395000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5146740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5156380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5170965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5171320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5172180000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5172520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5172920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5173820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5174160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5174500000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5174820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5175240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5175705000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5175780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5176900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5177220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5177640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5179380000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5179720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180040000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180380000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5180780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5181255000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5181320000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5184680000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5187690000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5190200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5193210000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5195580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5196360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5196700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5196780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5197560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5197900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5197980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5198760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5199100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5199180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5201040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5201380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5201460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5202240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5202580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5202660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5203440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5203780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5203860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5204640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5204980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5205060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5206920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5207860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5208180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5208260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5209020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5209960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5210280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5210360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5211120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5212060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5212380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5212460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5213220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5214160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5214480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5214560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5216400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5217340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5217915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5217980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5218740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5219680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5220255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5220320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5221080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5222020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5222595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5222660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5223420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5224360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5224935000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5225000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5225445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5225775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5226105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5226435000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5226765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5227095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5227425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5229600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5230725000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5231080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5232320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5233305000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5233660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5235040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5236575000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5236920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5246560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5261145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5261500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5262360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5262700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5263100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5264000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5264340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5264680000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5265000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5265420000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5265885000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5265960000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5267080000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5267400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5267820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5269560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5269900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5270220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5270560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5270960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5271435000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5271500000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5274860000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5277870000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5280380000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5283390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5285340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5285680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5285760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5286540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5286880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5286960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5287740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5288080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5288160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5288940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5289280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5289360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5291220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5291560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5291640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5292420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5292760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5292840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5293620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5293960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5294040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5294820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5295160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5295240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5297100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5298040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5298360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5298440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5299200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5300140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5300460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5300540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5301300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5302240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5302560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5302640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5303400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5304340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5304660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5304740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5306580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5307520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5308095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5308160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5308920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5309860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5310435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5310500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5311260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5312200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5312775000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5312840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5313600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5314540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5315115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5315180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5315625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5315955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5316285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5316615000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5316945000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5317275000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5317605000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5319780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5320905000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5321260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5322500000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5323485000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5323840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5325220000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5326755000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5327100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5336740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5351325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5351680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5352540000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5352880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5353280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5354180000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5354520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5354860000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5355180000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5355600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5356065000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5356140000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5357260000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5357580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5358000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5359740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5360080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5360400000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5360740000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5361140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5361615000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5361680000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5365040000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5368050000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5370560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5373570000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5375520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5375860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5375940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5376720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5377060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5377140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5377920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5378260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5378340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5379120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5379460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5379540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5381400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5381740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5381820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5382600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5382940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5383020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5383800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5384140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5384220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5385000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5385340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5385420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5387280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5388220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5388540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5388620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5389380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5390320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5390640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5390720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5391480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5392420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5392740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5392820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5393580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5394520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5394840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5394920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5396760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5397700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5398275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5398340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5399100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5400040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5400615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5400680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5401440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5402380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5402955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5403020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5403780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5404720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5405295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5405360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5405805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5406135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5406465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5406795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5407125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5407455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5407785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5409960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5411085000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5411440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5412680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5413665000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5414020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5415400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5416935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5417280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5426920000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5441505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5441860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5442720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5443060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5443460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5444360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5444700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5445040000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5445360000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5445780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5446245000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5446320000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5447440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5447760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5448180000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5449920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5450260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5450580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5450920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5451320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5451795000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5451860000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5455220000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5458230000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5460740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5463750000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5465700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5466040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5466120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5466900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5467240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5467320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5468100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5468440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5468520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5469300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5469640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5469720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5471580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5471920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5472000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5472780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5473120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5473200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5473980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5474320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5474400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5475180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5475520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5475600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5477460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5478400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5478720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5478800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5479560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5480500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5480820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5480900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5481660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5482600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5482920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5483000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5483760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5484700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5485020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5485100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5486940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5487880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5488455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5488520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5489280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5490220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5490795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5490860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5491620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5492560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5493135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5493200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5493960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5494900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5495475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5495540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5495985000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5496315000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5496645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5496975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5497305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5497635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5497965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5500425000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5501115000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5501460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5502105000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5502795000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5503140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5503785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5504475000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5504820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5505645000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5506335000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5506680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5507775000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5508435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5508780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5509875000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5510535000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5510880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5512395000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5513055000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5513400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5514915000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5515575000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5515920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5516955000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5517300000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5519655000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5520315000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5520660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5532200000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5540740000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5558920000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5562060000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5563065000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5573420000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5582320000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5583525000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5584605000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5585100000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5585460000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5585820000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5586675000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5587455000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5588235000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5590160000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5590520000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5591385000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5592165000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5593695000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5593905000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5594115000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5594325000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5594535000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5594745000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5594955000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5595165000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5595375000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5595585000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5595795000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5596005000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5596215000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5596815000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5597160000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5602155000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5605845000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5607620000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5614100000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5617410000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5653095000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5653740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5654175000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5654820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5656035000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5656665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5657385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5658075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5658765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5660260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5660260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5660260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5660260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5660980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5662240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5662240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5662240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5662240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5662960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5664580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5664580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5664580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5664580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5665480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5666205000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5666920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5667640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5668845000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5669560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5671695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5672340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5672775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5673420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5674635000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5675265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5675985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5676675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5677365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5678860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5678860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5678860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5678860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5679580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5680840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5680840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5680840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5680840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5681560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5683180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5683180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5683180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5683180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5684080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5684805000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5685520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5686240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5687445000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5688160000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5690295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5690940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5691375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5692020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5693235000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5693865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5694585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5695275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5695965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5697460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5697460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5697460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5697460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5698180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5699440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5699440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5699440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5699440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5700160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5701780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5701780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5701780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5701780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5702680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5703405000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5704120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5704840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5706045000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5706760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5708760000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5708940000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5709140000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5710660000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5710840000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5710940000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5711040000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5711640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5711840000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5711960000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5712080000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5715255000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5715680000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5715760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5716100000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5717625000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5719100000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5720060000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5720400000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5724680000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5725040000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5726760000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5727120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5729000000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5729360000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5731575000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5731905000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5732480000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5732840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5733200000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5733560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5734815000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5735180000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5735900000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5736260000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5738385000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5738760000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5739480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5739560000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5740560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5741540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5742620000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5742980000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5743340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5743980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5744740000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5745080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5746400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5747580000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5747940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5749060000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5749785000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5750160000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5750880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5751240000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5752100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5756355000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5756780000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5757555000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5757980000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5758665000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5759180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5760420000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5760600000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5760960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5761580000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5762040000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5762740000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5762900000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5763260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5763900000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5765100000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5765460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5765820000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5766645000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5767020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5767695000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5768025000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5768400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5768955000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5769140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5769500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5770140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5770757000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5770940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5771300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5771940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5772615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5772800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5773160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5773800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5774355000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5774540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5774900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5775540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5776095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5776280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5776640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5777280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5778105000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5778300000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5778660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5779280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5779965000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5780295000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5780660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5781225000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5781420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5781780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5782365000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5782560000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5782920000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5783540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5785425000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5785620000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5785980000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5786600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5787585000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5787780000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5788140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5788760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5792655000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5792895000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5793135000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5793735000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5794005000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5794245000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5794845000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5795085000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5795685000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5796405000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5796675000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5797425000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5797665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5798415000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5806275000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5806545000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5806845000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5807145000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5809095000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5826560000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5827640000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5831760000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5832540000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5833260000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5834020000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5835280000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5836000000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5841220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5842120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5843020000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5844375000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5846500000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5847440000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5848420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5849280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5849880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5885745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5886360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5886825000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5887440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5888685000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5889375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5890095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5890785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5891475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5893120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5893120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5893120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5893120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5893840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5895280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5895280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5895280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5895280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5896000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5897620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5897620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5897620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5897620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5898520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5899245000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5899960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5900680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5901885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5902600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5904765000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5905380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5905845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5906460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5907705000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5908395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5909115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5909805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5910495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5912140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5912140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5912140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5912140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5912860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5914300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5914300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5914300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5914300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5915020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5916640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5916640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5916640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5916640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5917540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5918265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5918980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5919700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5920905000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5921620000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5923785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5924400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5924865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5925480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5926725000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5927415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5928135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5928825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5929515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5931160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5931160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5931160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5931160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5931880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5933320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5933320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5933320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5933320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5934040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5935660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5935660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5935660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5935660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5936560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5937285000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5938000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5938720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5939925000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5940640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5942640000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5942820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5943020000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5944540000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5944720000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5944820000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5944920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5945520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5945720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5945840000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5945960000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5949135000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5949560000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5949640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5949980000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5951505000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5952980000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5953940000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5954280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5958560000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5958920000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5960640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5961000000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5962880000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5963240000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5965485000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5965845000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5966540000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5966900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5967260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5967620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5968905000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5969280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5970000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5970360000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5972505000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5972880000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5973600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5973680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5974680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5975660000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5976740000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5977100000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5977460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5978100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5978860000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5979200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5980520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5981700000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5982060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5983360000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5984085000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5984460000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5985180000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5985540000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5986400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5990685000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5991120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5991915000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5992340000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5993055000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5993580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5994780000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5994960000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5995320000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5995940000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5996400000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5997100000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5997260000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5997620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5998260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5999460000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 5999820000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6000180000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6001035000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6001400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6002085000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6002415000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6002780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6003345000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6003540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6003900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6004520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6005177000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6005360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6005720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6006360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6007035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6007220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6007580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6008220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6008775000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6008960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6009320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6009960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6010515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6010700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6011060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6011700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6012555000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6012740000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6013100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6013740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6014415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6014745000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6015120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6015675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6015860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6016220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6016845000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6017040000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6017400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6018020000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6019905000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6020100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6020460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6021080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6022065000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6022260000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6022620000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6023240000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6027165000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6027435000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6027705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6028335000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6028635000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6028905000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6029535000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6029805000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6030435000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6031185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6031485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6032265000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6032535000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6033315000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6041205000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6041505000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6041835000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6042165000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6044145000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6063440000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6064520000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6068640000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6069420000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6070140000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6071080000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6072520000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6073240000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6078460000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6079360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6080260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6081645000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6083780000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6084720000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6085680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6086520000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6087120000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6123015000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6123600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6124095000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6124680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6125955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6126645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6127365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6128055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6128745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6130360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6130360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6130360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6130360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6131260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6132700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6132700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6132700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6132700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6133600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6135400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6135400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6135400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6135400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6136300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6137025000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6137740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6138460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6139665000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6140380000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6142575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6143160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6143655000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6144240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6145515000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6146205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6146925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6147615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6148305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6149920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6149920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6149920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6149920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6150820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6152260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6152260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6152260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6152260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6153160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6154960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6154960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6154960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6154960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6155860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6156585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6157300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6158020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6159225000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6159940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6162135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6162720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6163215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6163800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6165075000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6165765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6166485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6167175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6167865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6169480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6169480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6169480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6169480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6170380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6171820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6171820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6171820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6171820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6172720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6174520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6174520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6174520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6174520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6175420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6176145000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6176860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6177580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6178785000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6179500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6181500000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6181680000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6181880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6183400000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6183580000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6183680000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6183780000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6184380000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6184580000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6184700000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6184820000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6187995000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6188420000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6188500000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6188840000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6190365000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6191840000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6192800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6193140000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6197600000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6197960000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6199680000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6200040000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6201920000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6202280000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6204555000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6204945000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6205580000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6205940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6206300000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6206660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6207975000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6208340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6209060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6209420000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6211665000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6212040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6212760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6212840000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6213840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6214820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6215900000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6216260000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6216620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6217260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6218020000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6218360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6219680000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6220860000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6221220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6222520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6223245000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6223620000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6224340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6224700000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6225560000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6229875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6230300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6231135000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6231560000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6232305000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6232820000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6234060000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6234240000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6234600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6235220000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6235680000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6236380000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6236540000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6236900000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6237540000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6238740000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6239100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6239460000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6240345000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6240720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6241395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6241725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6242100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6242655000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6242840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6243200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6243840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6244517000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6244700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6245060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6245700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6246375000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6246560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6246920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6247560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6248115000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6248300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6248660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6249300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6249855000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6250040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6250400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6251040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6251925000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6252120000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6252480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6253100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6253785000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6254115000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6254480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6255045000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6255240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6255600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6256245000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6256440000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6256800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6257420000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6259305000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6259500000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6259860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6260480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6261465000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6261660000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6262020000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6262640000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6266775000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6267075000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6267375000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6268035000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6268365000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6268665000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6269325000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6269625000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6270285000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6271065000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6271395000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6272205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6272505000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6273315000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6281235000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6281565000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6281925000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6282285000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6284295000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6303620000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6304700000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6308820000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6309700000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6310420000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6311360000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6312800000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6313700000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6319060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6319960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6320860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6322275000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6324580000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6325520000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6326500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6327360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6327960000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6363885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6364620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6365145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6365880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6367185000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6367935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6368655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6369525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6370215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6371800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6371800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6371800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6371800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6372700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6374140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6374140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6374140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6374140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6375040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6376840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6376840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6376840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6376840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6377740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6378465000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6379180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6379900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6381105000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6381820000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6384045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6384780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6385305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6386040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6387345000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6388095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6388815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6389685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6390375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6391960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6391960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6391960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6391960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6392860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6394300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6394300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6394300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6394300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6395200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6397000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6397000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6397000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6397000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6397900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6398625000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6399340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6400060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6401265000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6401980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6404205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6404940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6405465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6406200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6407505000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6408255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6408975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6409845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6410535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6412120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6412120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6412120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6412120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6413020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6414460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6414460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6414460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6414460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6415360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6417160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6417160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6417160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6417160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6418060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6418785000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6419500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6420220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6421425000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6422140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6424140000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6424320000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6424520000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6426040000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6426220000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6426320000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6426420000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6427020000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6427220000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6427340000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6427460000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6430635000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6431060000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6431140000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6431480000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6433005000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6434480000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6435440000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6435780000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6440240000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6440600000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6442320000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6442680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6444560000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6444920000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6447225000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6447645000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6448400000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6448760000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6449120000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6449480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6450825000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6451200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6451920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6452280000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6454545000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6454920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6455640000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6455720000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6456720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6457700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6458780000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6459140000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6459500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6460140000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6461080000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6461420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6462740000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6463920000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6464280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6465580000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6466305000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6466680000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6467400000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6467760000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6468620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6472965000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6473400000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6474255000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6474680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6475455000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6475980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6477180000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6477360000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6477720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6478340000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6478800000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6479680000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6479840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6480200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6480840000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6482040000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6482400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6482760000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6483675000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6484040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6484725000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6485055000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6485420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6485985000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6486180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6486540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6487160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6487877000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6488060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6488420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6489060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6489735000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6489920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6490280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6490920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6491475000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6491660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6492020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6492660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6493215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6493400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6493760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6494400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6495315000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6495500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6495860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6496500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6497175000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6497505000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6497880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6498435000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6498620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6498980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6499665000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6499860000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6500220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6500840000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6502725000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6502920000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6503280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6503900000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6504885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6505080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6505440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6506060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6510225000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6510555000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6510885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6511575000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6511935000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6512265000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6512955000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6513285000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6513975000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6514785000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6515145000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6515985000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6516315000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6517155000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6525105000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6525465000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6525855000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6526245000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6528285000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6547640000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6548900000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6553300000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6554180000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6555080000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6556020000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6557440000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6558340000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6563680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6564580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6565480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6566925000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6569240000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6570180000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6571140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6571980000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6572580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6575480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6576285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6576660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6577760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6578505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6578880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6580020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6580935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6581300000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6585440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6594645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6595020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6595820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6596180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6596620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6597480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6597840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6598200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6598560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6599000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6599475000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6599540000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6600420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6600780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6601220000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6602340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6602700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6603060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6603420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6603860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6604335000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6604400000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6607500000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6610320000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6612560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6615390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6617360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6617720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6617800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6618500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6618860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6618940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6619640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6620000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6620080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6620780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6621140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6621220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6623060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6623420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6623500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6624200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6624560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6624640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6625340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6625700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6625780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6626480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6626840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6626920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6628760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6629760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6630120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6630200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6630920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6631920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6632280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6632360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6633080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6634080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6634440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6634520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6635240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6636240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6636600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6636680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6638540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6639540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6640155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6640220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6640940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6641940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6642555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6642620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6643340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6644340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6644955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6645020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6645740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6646740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6647355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6647420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6647865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6648195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6648525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6648855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6649185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6649515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6649845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6651980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6652785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6653160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6654260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6655005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6655380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6656520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6657435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6657800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6661940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6671145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6671520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6672320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6672680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6673120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6673980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6674340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6674700000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6675060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6675500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6675975000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6676040000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6676920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6677280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6677720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6678840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6679200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6679560000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6679920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6680360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6680835000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6680900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6684000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6686820000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6689060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6691890000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6693860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6694220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6694300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6695000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6695360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6695440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6696140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6696500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6696580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6697280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6697640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6697720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6699560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6699920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6700000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6700700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6701060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6701140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6701840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6702200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6702280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6702980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6703340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6703420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6705260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6706260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6706620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6706700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6707420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6708420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6708780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6708860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6709580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6710580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6710940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6711020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6711740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6712740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6713100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6713180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6715040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6716040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6716655000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6716720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6717440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6718440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6719055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6719120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6719840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6720840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6721455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6721520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6722240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6723240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6723855000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6723920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6724365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6724695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6725025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6725355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6725685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6726015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6726345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6728480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6729285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6729660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6730760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6731505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6731880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6733020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6733935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6734300000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6738440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6747645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6748020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6748820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6749180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6749620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6750480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6750840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6751200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6751560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6752000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6752475000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6752540000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6753420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6753780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6754220000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6755340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6755700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6756060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6756420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6756860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6757335000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6757400000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6760500000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6763320000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6765560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6768390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6770360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6770720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6770800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6771500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6771860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6771940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6772640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6773000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6773080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6773780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6774140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6774220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6776060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6776420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6776500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6777200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6777560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6777640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6778340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6778700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6778780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6779480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6779840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6779920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6781760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6782760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6783120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6783200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6783920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6784920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6785280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6785360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6786080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6787080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6787440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6787520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6788240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6789240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6789600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6789680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6791540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6792540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6793155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6793220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6793940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6794940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6795555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6795620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6796340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6797340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6797955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6798020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6798740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6799740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6800355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6800420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6800865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6801195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6801525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6801855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6802185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6802515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6802845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6804980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6805785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6806160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6807260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6808005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6808380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6809520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6810435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6810800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6814940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6824145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6824520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6825320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6825680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6826120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6826980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6827340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6827700000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6828060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6828500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6828975000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6829040000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6829920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6830280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6830720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6831840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6832200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6832560000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6832920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6833360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6833835000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6833900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6837000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6839820000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6842060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6844890000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6846860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6847220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6847300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6848000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6848360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6848440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6849140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6849500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6849580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6850280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6850640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6850720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6852560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6852920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6853000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6853700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6854060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6854140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6854840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6855200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6855280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6855980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6856340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6856420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6858260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6859260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6859620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6859700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6860420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6861420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6861780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6861860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6862580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6863580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6863940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6864020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6864740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6865740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6866100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6866180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6868040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6869040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6869655000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6869720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6870440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6871440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6872055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6872120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6872840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6873840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6874455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6874520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6875240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6876240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6876855000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6876920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6877365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6877695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6878025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6878355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6878685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6879015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6879345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6881775000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6882465000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6882840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6883425000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6884145000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6884520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6885105000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6885825000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6886200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6886905000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6887625000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6888000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6888765000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6889485000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6889860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6890655000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6891345000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6891720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6892635000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6893325000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6893700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6894645000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6895365000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6895740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6896475000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6896840000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6899175000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6899865000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6900240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6906340000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6909560000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6916420000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6919680000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6920625000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6925460000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6928820000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6929715000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6930465000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6930900000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6931200000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6931500000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6932265000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6932955000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6933645000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6935540000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6935840000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6936615000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6937305000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6938865000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6939075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6939285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6939495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6939705000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6939915000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6940125000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6940335000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6940545000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6940755000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6940965000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6941175000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6941385000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6942015000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6942380000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6947415000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6950865000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6952240000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6958760000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6961950000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6993795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6994200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6994635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6995040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6996435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6997005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6997665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6998235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 6998805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7000300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7000300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7000300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7000300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7000900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7002240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7002240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7002240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7002240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7002840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7005860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7005860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7005860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7005860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7006580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7007265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7007860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7008460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7009515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7010100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7011795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7012200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7012635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7013040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7014435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7015005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7015665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7016235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7016805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7018300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7018300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7018300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7018300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7018900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7020240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7020240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7020240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7020240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7020840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7023860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7023860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7023860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7023860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7024580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7025265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7025860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7026460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7027515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7028100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7029795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7030200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7030635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7031040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7032435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7033005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7033665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7034235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7034805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7036300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7036300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7036300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7036300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7036900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7038240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7038240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7038240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7038240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7038840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7041860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7041860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7041860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7041860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7042580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7043265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7043860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7044460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7045515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7046100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7047540000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7047660000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7047900000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7048920000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049040000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049160000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049280000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049700000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049840000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7049980000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7050120000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7052715000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7053080000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7053160000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7053440000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7054635000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7055900000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7056680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7056960000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7061020000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7061300000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7062740000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7063040000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7064700000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7065000000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7066815000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7067115000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7067540000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7067840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7068140000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7068440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7069395000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7069700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7070300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7070600000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7072725000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7073040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7073640000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7073720000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7074540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7075340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7076240000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7076540000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7076840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7077360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7078120000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7078400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7079700000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7080940000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7081220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7082520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7083195000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7083500000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7084100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7084400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7085120000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7088625000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7089000000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7089705000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7090080000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7090695000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7091160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7092120000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7092300000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7092600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7093100000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7093500000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7094080000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7094240000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7094540000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7095060000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7096020000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7096320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7096620000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7097295000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7097600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7098225000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7098555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7098860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7099365000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7099560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7099860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7100360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7100897000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7101080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7101380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7101900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7102515000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7102700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7103000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7103520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7104015000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7104200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7104500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7105020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7105515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7105700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7106000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7106520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7107195000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7107380000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7107680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7108200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7108815000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7109145000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7109460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7109955000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7110140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7110440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7110945000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7111140000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7111440000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7111940000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7113435000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7113620000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7113920000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7114440000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7115295000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7115480000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7115780000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7116300000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7119375000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7119585000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7119795000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7120305000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7120545000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7120755000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7121385000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7121595000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7122225000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7122765000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7123125000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7123815000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7124025000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7124835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7127745000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7127985000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7128375000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7128765000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7137525000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7156480000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7157320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7161740000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7162560000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7163280000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7164440000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7165780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7166380000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7173500000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7174320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7175120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7176105000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7179720000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7180580000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7181500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7182300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7182900000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7214685000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7215180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7215645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7216140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7217565000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7218195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7218855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7219515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7220205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7221760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7221760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7221760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7221760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7222360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7223700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7223700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7223700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7223700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7224300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7227320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7227320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7227320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7227320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7228040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7228725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7229320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7229920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7230975000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7231560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7233285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7233780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7234245000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7234740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7236165000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7236795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7237455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7238115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7238805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7240360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7240360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7240360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7240360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7240960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7242300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7242300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7242300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7242300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7242900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7245920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7245920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7245920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7245920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7246640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7247325000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7247920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7248520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7249575000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7250160000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7251885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7252380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7252845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7253340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7254765000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7255395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7256055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7256715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7257405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7258960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7258960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7258960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7258960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7259560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7260900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7260900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7260900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7260900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7261500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7264520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7264520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7264520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7264520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7265240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7265925000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7266520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7267120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7268175000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7268760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7270200000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7270320000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7270560000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7271580000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7271700000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7271820000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7271940000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7272360000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7272500000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7272640000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7272780000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7275375000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7275740000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7275820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7276100000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7277295000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7278560000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7279340000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7279620000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7283780000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7284080000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7285640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7285940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7287600000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7287900000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7289745000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7290075000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7290560000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7290860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7291160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7291460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7292445000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7292760000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7293360000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7293660000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7295805000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7296120000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7296720000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7296800000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7297620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7298420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7299320000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7299620000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7299920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7300440000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7301200000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7301480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7302780000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7304020000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7304300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7305600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7306275000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7306580000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7307180000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7307480000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7308200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7311735000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7312100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7312845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7313220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7313865000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7314320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7315320000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7315500000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7315800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7316300000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7316700000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7317280000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7317440000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7317740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7318260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7319220000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7319520000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7319820000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7320525000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7320840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7321455000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7321785000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7322100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7322595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7322780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7323080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7323600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7324157000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7324340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7324640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7325160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7325775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7325960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7326260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7326780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7327275000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7327460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7327760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7328280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7328775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7328960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7329260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7329780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7330485000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7330680000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7330980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7331480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7332105000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7332435000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7332740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7333245000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7333440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7333740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7334265000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7334460000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7334760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7335260000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7336755000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7336940000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7337240000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7337760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7338615000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7338800000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7339100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7339620000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7342725000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7342965000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7343205000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7343745000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7344015000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7344255000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7344915000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7345155000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7345815000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7346385000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7346775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7347495000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7347735000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7348575000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7351515000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7351785000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7352205000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7352625000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7361415000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7380420000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7381380000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7385920000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7386740000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7387460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7388620000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7389960000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7390560000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7397840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7398660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7399460000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7400475000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7404180000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7405040000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7405960000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7406760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7407360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7439415000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7439880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7440375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7440840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7442295000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7442925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7443585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7444245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7444935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7446560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7446560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7446560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7446560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7447280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7448720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7448720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7448720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7448720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7449440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7452480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7452480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7452480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7452480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7453200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7453875000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7454460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7455060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7456095000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7456680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7458435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7458900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7459395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7459860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7461315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7461945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7462605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7463265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7463955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7465580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7465580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7465580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7465580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7466300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7467740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7467740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7467740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7467740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7468460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7471500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7471500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7471500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7471500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7472220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7472895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7473480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7474080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7475115000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7475700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7477455000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7477920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7478415000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7478880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7480335000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7480965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7481625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7482285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7482975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7484600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7484600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7484600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7484600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7485320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7486760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7486760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7486760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7486760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7487480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7490520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7490520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7490520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7490520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7491240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7491915000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7492500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7493100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7494135000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7494720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7496160000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7496280000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7496520000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7497540000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7497660000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7497780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7497900000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7498320000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7498460000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7498600000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7498740000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7501335000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7501700000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7501780000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7502060000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7503255000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7504520000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7505300000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7505580000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7509740000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7510040000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7511600000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7511900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7513560000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7513860000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7515735000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7516095000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7516640000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7516940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7517240000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7517540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7518555000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7518860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7519460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7519760000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7522005000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7522320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7522920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7523000000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7523820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7524620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7525640000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7525940000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7526240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7526760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7527620000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7527920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7529320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7530660000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7530960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7532340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7533015000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7533320000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7533920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7534220000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7534940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7538505000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7538880000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7539645000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7540020000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7540695000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7541160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7542120000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7542300000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7542600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7543100000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7543500000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7544080000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7544240000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7544540000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7545060000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7546020000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7546320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7546620000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7547355000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7547660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7548285000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7548615000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7548920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7549425000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7549620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7549920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7550420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7551017000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7551200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7551500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7552020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7552635000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7552820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7553120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7553640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7554135000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7554320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7554620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7555140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7555635000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7555820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7556120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7556640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7557375000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7557560000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7557860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7558380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7558995000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7559325000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7559640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7560135000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7560320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7560620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7561185000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7561380000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7561680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7562180000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7563675000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7563860000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7564160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7564680000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7565535000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7565720000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7566020000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7566540000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7569855000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7570125000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7570395000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7570965000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7571265000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7571535000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7572225000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7572495000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7573185000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7573785000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7574205000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7574955000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7575225000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7576095000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7579065000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7579365000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7579815000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7580265000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7589085000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7608040000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7609000000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7613660000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7614600000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7615320000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7616480000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7617920000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7618640000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7625960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7626780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7627580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7628625000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7632440000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7633300000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7634220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7635000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7635600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7667805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7668360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7668885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7669440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7670925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7671615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7672365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7673055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7673715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7675300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7675300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7675300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7675300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7676020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7677460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7677460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7677460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7677460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7678180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7681320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7681320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7681320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7681320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7682040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7682715000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7683300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7683900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7684935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7685520000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7687305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7687860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7688385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7688940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7690425000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7691115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7691865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7692555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7693215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7694800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7694800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7694800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7694800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7695520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7696960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7696960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7696960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7696960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7697680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7700820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7700820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7700820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7700820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7701540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7702215000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7702800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7703400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7704435000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7705020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7706805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7707360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7707885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7708440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7709925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7710615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7711365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7712055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7712715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7714300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7714300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7714300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7714300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7715020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7716460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7716460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7716460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7716460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7717180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7720320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7720320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7720320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7720320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7721040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7721715000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7722300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7722900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7723935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7724520000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7725960000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7726080000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7726320000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7727340000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7727460000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7727580000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7727700000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7728120000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7728260000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7728400000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7728540000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7731135000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7731500000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7731580000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7731860000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7733055000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7734320000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7735100000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7735380000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7739780000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7740080000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7741640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7741940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7743740000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7744040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7746105000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7746495000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7747100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7747400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7747700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7748000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7749045000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7749360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7749960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7750260000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7752525000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7752840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7753440000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7753520000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7754340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7755140000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7756160000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7756460000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7756760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7757280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7758140000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7758440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7759840000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7761180000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7761480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7762860000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7763535000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7763840000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7764440000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7764740000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7765460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7769055000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7769420000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7770225000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7770600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7771305000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7771760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7772880000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7773060000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7773360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7773860000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7774260000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7774960000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7775120000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7775420000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7775940000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7777020000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7777320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7777620000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7778385000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7778700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7779315000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7779645000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7779960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7780455000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7780640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7780940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7781460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7782077000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7782260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7782560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7783080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7783695000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7783880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7784180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7784700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7785195000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7785380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7785680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7786200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7786695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7786880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7787180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7787700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7788465000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7788660000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7788960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7789460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7790085000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7790415000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7790720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7791225000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7791420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7791720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7792305000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7792500000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7792800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7793300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7794795000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7794980000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7795280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7795800000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7796655000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7796840000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7797140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7797660000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7801005000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7801305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7801605000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7802205000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7802535000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7802835000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7803555000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7803855000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7804575000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7805205000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7805655000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7806435000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7806735000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7807635000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7810635000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7810965000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7811445000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7811925000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7820775000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7841280000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7842360000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7847140000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7848080000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7848920000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7850080000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7851520000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7852240000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7859640000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7860540000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7861440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7862505000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7866320000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7867280000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7868200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7869000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7869600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7871820000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7872885000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7873200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7874200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7874955000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7875260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7876480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7878045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7878360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7889560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7904385000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7904700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7905360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7905660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7906040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7906820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7907120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7907420000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7907720000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7908100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7908495000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7908560000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7909540000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7909820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7910200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7912040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7912340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7912640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7912940000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7913320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7913715000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7913780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7916360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7919100000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7921080000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7923810000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7925480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7925780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7925860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7926500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7926800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7926880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7927520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7927820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7927900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7928540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7928840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7928920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7930460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7930760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7930840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7931480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7931780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7931860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7932500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7932800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7932880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7933520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7933820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7933900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7935440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7936260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7936560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7936640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7937300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7938120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7938420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7938500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7939160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7939980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7940280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7940360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7941020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7941840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7942140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7942220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7943780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7944600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7945095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7945160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7945820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7946640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7947135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7947200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7947860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7948680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7949175000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7949240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7949900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7950720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7951215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7951280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7951725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7952055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7952385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7952715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7953045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7953375000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7953705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7955400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7956465000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7956780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7957780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7958535000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7958840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7960060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7961625000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7961940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7973140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7987965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7988280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7988940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7989240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7989620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7990400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7990700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7991000000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7991300000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7991680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7992075000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7992140000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7993120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7993400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7993780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7995620000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7995920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7996220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7996520000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7996900000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7997295000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7997360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 7999940000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8002680000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8004660000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8007390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8009060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8009360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8009440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8010080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8010380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8010460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8011100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8011400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8011480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8012120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8012420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8012500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8014040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8014340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8014420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8015060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8015360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8015440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8016080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8016380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8016460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8017100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8017400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8017480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8019020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8019840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8020140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8020220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8020880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8021700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8022000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8022080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8022740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8023560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8023860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8023940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8024600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8025420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8025720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8025800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8027360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8028180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8028675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8028740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8029400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8030220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8030715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8030780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8031440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8032260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8032755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8032820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8033480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8034300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8034795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8034860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8035305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8035635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8035965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8036295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8036625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8036955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8037285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8038980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8040045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8040360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8041360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8042115000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8042420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8043640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8045205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8045520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8056720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8071545000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8071860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8072520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8072820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8073200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8073980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8074280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8074580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8074880000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8075260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8075655000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8075720000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8076700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8076980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8077360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8079200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8079500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8079800000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8080100000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8080480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8080875000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8080940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8083520000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8086260000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8088240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8090970000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8092640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8092940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8093020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8093660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8093960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8094040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8094680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8094980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8095060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8095700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8096000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8096080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8097620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8097920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8098000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8098640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8098940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8099020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8099660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8099960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8100040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8100680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8100980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8101060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8102600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8103420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8103720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8103800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8104460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8105280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8105580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8105660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8106320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8107140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8107440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8107520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8108180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8109000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8109300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8109380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8110940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8111760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8112255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8112320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8112980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8113800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8114295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8114360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8115020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8115840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8116335000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8116400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8117060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8117880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8118375000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8118440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8118885000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8119215000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8119545000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8119875000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8120205000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8120535000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8120865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8122560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8123625000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8123940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8124940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8125695000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8126000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8127220000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8128785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8129100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8140300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8155125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8155440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8156100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8156400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8156780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8157560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8157860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8158160000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8158460000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8158840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8159235000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8159300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8160280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8160560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8160940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8162780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8163080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8163380000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8163680000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8164060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8164455000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8164520000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8167100000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8169840000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8171820000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8174550000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8176220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8176520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8176600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8177240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8177540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8177620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8178260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8178560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8178640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8179280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8179580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8179660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8181200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8181500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8181580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8182220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8182520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8182600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8183240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8183540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8183620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8184260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8184560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8184640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8186180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8187000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8187300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8187380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8188040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8188860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8189160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8189240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8189900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8190720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8191020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8191100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8191760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8192580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8192880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8192960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8194520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8195340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8195835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8195900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8196560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8197380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8197875000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8197940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8198600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8199420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8199915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8199980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8200640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8201460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8201955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8202020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8202465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8202795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8203125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8203455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8203785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8204115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8204445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8206425000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8207025000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8207340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8207895000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8208465000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8208780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8209335000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8209905000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8210220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8210835000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8211405000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8211720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8212695000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8213265000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8213580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8214555000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8215125000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8215440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8216925000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8217525000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8217840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8219325000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8219925000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8220240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8221155000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8221460000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8223345000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8223945000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8224260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8237080000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8247100000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8268520000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8271140000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8271975000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8283700000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8294320000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8295495000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8296545000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8297025000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8297415000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8297805000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8298645000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8299395000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8300145000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8301735000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8302125000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8302965000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8303715000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8304945000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8305155000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8305365000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8305575000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8305785000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8305995000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8306205000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8306415000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8306625000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8306835000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8307045000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8307255000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8307465000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8307975000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8308280000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8312415000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8316105000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8318040000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8323940000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8326890000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8359815000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8360360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8360775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8361200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8362545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8363145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8363775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8364345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8364945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8366440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8366440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8366440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8366440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8367140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8368500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8368500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8368500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8368500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8369200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8371860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8371860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8371860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8371860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8372560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8373255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8373800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8374500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8375625000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8376180000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8378085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8378640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8379075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8379620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8380965000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8381565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8382195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8382765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8383365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8384860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8384860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8384860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8384860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8385560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8386920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8386920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8386920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8386920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8387620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8390280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8390280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8390280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8390280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8390980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8391675000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8392220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8392920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8394045000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8394600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8396505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8397060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8397495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8398040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8399385000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8399985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8400615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8401185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8401785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8403280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8403280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8403280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8403280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8403980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8405340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8405340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8405340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8405340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8406040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8408700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8408700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8408700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8408700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8409400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8410095000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8410640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8411340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8412465000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8413020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8414700000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8414840000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8415080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8416280000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8416420000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8416540000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8416660000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8417140000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8417300000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8417440000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8417580000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8420355000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8420740000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8420820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8421140000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8422425000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8423680000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8424500000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8424800000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8428880000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8429200000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8430560000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8430880000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8432480000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8432800000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8434665000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8434965000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8435440000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8435740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8436040000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8436340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8437365000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8437700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8438320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8438620000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8440755000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8441080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8441680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8441760000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8442640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8443480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8444340000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8444660000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8444980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8445520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8446300000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8446600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8447880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8449020000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8449340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8450640000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8451345000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8451680000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8452300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8452600000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8453360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8456955000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8457340000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8458065000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8458460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8459115000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8459600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8460600000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8460780000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8461100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8461660000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8462060000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8462600000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8462780000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8463100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8463640000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8464620000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8464940000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8465260000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8465985000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8466320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8466975000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8467305000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8467640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8468175000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8468360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8468680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8469220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8469767000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8469960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8470280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8470840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8471475000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8471660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8471980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8472520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8473035000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8473220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8473540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8474080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8474595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8474780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8475100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8475640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8476365000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8476560000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8476880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8477440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8478075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8478405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8478740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8479275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8479460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8479780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8480295000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8480480000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8480800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8481340000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8482965000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8483160000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8483480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8484040000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8484975000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8485160000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8485480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8486020000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8489505000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8489715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8489925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8490465000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8490705000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8490915000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8491515000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8491725000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8492355000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8492925000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8493255000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8493945000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8494155000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8494935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8499075000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8499315000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8499675000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8500035000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8507085000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8524740000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8525580000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8529980000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8530820000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8531520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8532540000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8533900000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8534600000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8541220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8542020000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8542840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8543895000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8547060000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8547840000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8548780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8549580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8550180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8584005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8584520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8584965000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8585500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8586885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8587515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8588145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8588835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8589555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8591140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8591140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8591140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8591140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8591840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8593200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8593200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8593200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8593200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8593900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8596560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8596560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8596560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8596560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8597260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8597955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8598500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8599200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8600325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8600880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8602815000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8603340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8603805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8604320000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8605695000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8606325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8606955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8607675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8608365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8609940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8609940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8609940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8609940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8610640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8611980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8611980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8611980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8611980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8612680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8615340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8615340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8615340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8615340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8616040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8616735000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8617280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8617980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8619105000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8619660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8621595000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8622120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8622585000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8623100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8624475000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8625105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8625735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8626455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8627145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8628720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8628720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8628720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8628720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8629420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8630760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8630760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8630760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8630760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8631460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8634120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8634120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8634120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8634120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8634820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8635515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8636060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8636760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8637885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8638440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8640120000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8640260000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8640500000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8641700000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8641840000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8641960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8642080000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8642560000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8642720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8642860000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8643000000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8645925000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8646280000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8646360000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8646680000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8647965000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8649220000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8650040000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8650340000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8654600000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8654920000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8656580000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8656900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8658660000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8658980000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8661045000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8661375000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8661920000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8662240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8662540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8662840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8663895000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8664220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8664820000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8665120000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8667315000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8667640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8668240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8668320000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8669200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8670040000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8671040000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8671360000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8671660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8672200000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8672980000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8673280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8674560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8675820000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8676140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8677440000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8678145000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8678480000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8679100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8679400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8680160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8684115000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8684500000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8685255000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8685640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8686305000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8686780000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8687900000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8688080000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8688400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8688940000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8689340000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8690020000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8690180000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8690500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8691040000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8692160000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8692480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8692780000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8693535000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8693860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8694495000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8694825000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8695160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8695695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8695880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8696200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8696740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8697317000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8697500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8697820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8698360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8698995000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8699180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8699500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8700040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8700555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8700740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8701060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8701600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8702115000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8702300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8702620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8703160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8703915000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8704100000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8704420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8704960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8705595000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8705925000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8706260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8706795000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8706980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8707300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8707845000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8708040000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8708360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8708920000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8710545000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8710740000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8711060000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8711620000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8712555000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8712740000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8713060000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8713600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8717115000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8717355000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8717595000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8718135000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8718405000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8718645000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8719305000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8719545000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8720205000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8720835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8721195000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8721915000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8722155000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8722965000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8727135000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8727405000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8727795000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8728185000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8735265000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8754820000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8755800000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8760200000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8761040000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8761740000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8762760000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8764120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8764820000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8771560000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8772360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8773180000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8774265000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8777560000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8778460000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8779380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8780200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8780800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8814855000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8815340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8815815000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8816320000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8817735000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8818395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8819025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8819745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8820435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8821980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8821980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8821980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8821980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8822680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8824020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8824020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8824020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8824020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8824720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8827380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8827380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8827380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8827380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8828080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8828775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8829320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8830020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8831145000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8831700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8833665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8834160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8834655000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8835140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8836545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8837205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8837835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8838525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8839245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8840800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8840800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8840800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8840800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8841500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8842860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8842860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8842860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8842860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8843560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8846220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8846220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8846220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8846220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8846920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8847615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8848160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8848860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8849985000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8850540000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8852505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8853000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8853495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8853980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8855385000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8856045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8856675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8857365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8858085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8859640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8859640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8859640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8859640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8860340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8861700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8861700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8861700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8861700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8862400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8865060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8865060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8865060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8865060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8865760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8866455000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8867000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8867700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8868825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8869380000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8871060000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8871200000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8871440000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8872640000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8872780000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8872900000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8873020000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8873500000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8873660000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8873800000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8873940000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8876865000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8877220000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8877300000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8877620000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8878905000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8880160000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8880980000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8881280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8885540000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8885860000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8887520000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8887840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8889600000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8889920000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8892015000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8892375000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8892860000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8893180000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8893480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8893780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8894865000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8895200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8895820000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8896120000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8898375000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8898700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8899300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8899380000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8900260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8901100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8902100000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8902420000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8902720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8903260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8904040000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8904340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8905620000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8906880000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8907200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8908500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8909205000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8909540000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8910160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8910460000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8911220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8915205000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8915600000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8916405000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8916800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8917515000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8918000000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8919140000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8919320000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8919640000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8920180000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8920580000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8921260000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8921420000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8921740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8922280000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8923400000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8923720000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8924020000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8924805000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8925140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8925795000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8926125000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8926460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8926995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8927180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8927500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8928040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8928647000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8928840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8929160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8929720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8930355000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8930540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8930860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8931400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8931915000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8932100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8932420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8932960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8933475000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8933660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8933980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8934520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8935305000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8935500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8935820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8936380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8937015000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8937345000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8937680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8938215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8938400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8938720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8939295000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8939480000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8939800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8940340000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8941965000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8942160000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8942480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8943040000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8943975000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8944160000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8944480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8945020000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8948565000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8948835000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8949105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8949705000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8950005000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8950275000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8950935000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8951205000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8951895000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8952525000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8952915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8953665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8953935000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8954775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8958975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8959275000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8959695000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8960115000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8967225000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8986740000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8987720000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8992260000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8993100000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8993940000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8995080000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8996440000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 8997140000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9003880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9004680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9005500000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9006615000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9010020000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9010920000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9011860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9012660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9013260000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9047385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9047980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9048495000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9049100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9050535000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9051225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9051975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9052695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9053385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9055020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9055020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9055020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9055020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9055720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9057180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9057180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9057180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9057180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9057880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9060660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9060660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9060660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9060660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9061500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9062205000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9062760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9063320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9064455000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9065000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9067005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9067600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9068115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9068720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9070155000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9070845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9071595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9072315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9073005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9074640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9074640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9074640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9074640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9075340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9076800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9076800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9076800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9076800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9077500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9080280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9080280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9080280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9080280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9081120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9081825000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9082380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9082940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9084075000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9084620000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9086625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9087220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9087735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9088340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9089775000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9090465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9091215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9091935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9092625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9094260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9094260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9094260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9094260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9094960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9096420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9096420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9096420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9096420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9097120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9099900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9099900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9099900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9099900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9100740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9101445000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9102000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9102560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9103695000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9104240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9105940000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9106080000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9106320000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9107520000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9107660000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9107780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9107900000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9108380000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9108540000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9108680000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9108820000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9111735000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9112120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9112200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9112520000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9113805000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9115060000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9115880000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9116180000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9120560000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9120880000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9122540000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9122860000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9124620000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9124940000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9127065000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9127455000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9128020000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9128320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9128620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9128920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9130035000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9130360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9130960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9131260000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9133575000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9133900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9134500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9134580000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9135460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9136300000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9137300000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9137620000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9137920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9138460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9139360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9139660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9141060000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9142320000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9142640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9144060000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9144765000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9145100000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9145720000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9146020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9146780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9150795000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9151180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9151995000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9152380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9153105000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9153580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9154700000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9154880000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9155200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9155740000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9156140000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9156820000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9156980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9157300000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9157840000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9158960000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9159280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9159580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9160395000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9160720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9161355000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9161685000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9162020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9162555000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9162740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9163060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9163600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9164237000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9164420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9164740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9165280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9165915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9166100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9166420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9166960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9167475000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9167660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9167980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9168520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9169035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9169220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9169540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9170080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9170895000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9171080000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9171400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9171940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9172575000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9172905000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9173240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9173775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9173960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9174280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9174885000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9175080000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9175400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9175960000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9177585000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9177780000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9178100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9178660000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9179595000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9179780000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9180100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9180640000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9184215000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9184515000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9184815000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9185415000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9185745000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9186045000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9186765000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9187065000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9187785000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9188475000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9188895000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9189675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9189975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9190845000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9195075000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9195405000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9195855000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9196305000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9203445000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9223060000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9224180000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9228840000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9229680000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9230520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9231660000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9233140000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9233840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9240820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9241740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9242680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9243825000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9247240000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9248140000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9249060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9249880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9250480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9253020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9254235000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9254560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9255740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9256725000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9257060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9258460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9260265000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9260600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9273800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9290925000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9291260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9292040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9292360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9292740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9293600000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9293920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9294220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9294520000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9294900000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9295305000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9295380000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9296520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9296840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9297240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9299300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9299620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9299920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9300220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9300600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9301005000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9301080000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9304140000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9307050000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9309360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9312270000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9314080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9314380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9314460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9315160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9315460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9315540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9316240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9316540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9316620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9317320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9317620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9317700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9319420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9319720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9319800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9320500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9320800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9320880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9321580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9321880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9321960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9322660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9322960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9323040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9324760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9325600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9325900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9325980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9326680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9327520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9327820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9327900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9328600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9329440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9329740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9329820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9330520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9331360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9331660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9331740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9333460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9334300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9334815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9334880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9335620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9336460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9336975000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9337040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9337780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9338620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9339135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9339200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9339940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9340780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9341295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9341360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9341805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9342135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9342465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9342795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9343125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9343455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9343785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9345720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9346935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9347260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9348440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9349425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9349760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9351160000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9352965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9353300000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9366500000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9383625000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9383960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9384740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9385060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9385440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9386300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9386620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9386920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9387220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9387600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9388005000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9388080000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9389220000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9389540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9389940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9392000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9392320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9392620000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9392920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9393300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9393705000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9393780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9396840000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9399750000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9402060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9404970000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9406780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9407080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9407160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9407860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9408160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9408240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9408940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9409240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9409320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9410020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9410320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9410400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9412120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9412420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9412500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9413200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9413500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9413580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9414280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9414580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9414660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9415360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9415660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9415740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9417460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9418300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9418600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9418680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9419380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9420220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9420520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9420600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9421300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9422140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9422440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9422520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9423220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9424060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9424360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9424440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9426160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9427000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9427515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9427580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9428320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9429160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9429675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9429740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9430480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9431320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9431835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9431900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9432640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9433480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9433995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9434060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9434505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9434835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9435165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9435495000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9435825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9436155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9436485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9438420000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9439635000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9439960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9441140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9442125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9442460000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9443860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9445665000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9446000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9459200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9476325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9476660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9477440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9477760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9478140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9479000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9479320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9479620000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9479920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9480300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9480705000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9480780000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9481920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9482240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9482640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9484700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9485020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9485320000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9485620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9486000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9486405000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9486480000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9489540000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9492450000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9494760000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9497670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9499480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9499780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9499860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9500560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9500860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9500940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9501640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9501940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9502020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9502720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9503020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9503100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9504820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9505120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9505200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9505900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9506200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9506280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9506980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9507280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9507360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9508060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9508360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9508440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9510160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9511000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9511300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9511380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9512080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9512920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9513220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9513300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9514000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9514840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9515140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9515220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9515920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9516760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9517060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9517140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9518860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9519700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9520215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9520280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9521020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9521860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9522375000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9522440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9523180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9524020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9524535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9524600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9525340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9526180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9526695000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9526760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9527205000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9527535000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9527865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9528195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9528525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9528855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9529185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9531120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9532335000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9532660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9533840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9534825000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9535160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9536560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9538365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9538700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9551900000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9569025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9569360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9570140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9570460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9570840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9571700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9572020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9572320000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9572620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9573000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9573405000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9573480000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9574620000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9574940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9575340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9577400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9577720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9578020000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9578320000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9578700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9579105000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9579180000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9582240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9585150000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9587460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9590370000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9592180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9592480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9592560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9593260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9593560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9593640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9594340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9594640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9594720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9595420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9595720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9595800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9597520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9597820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9597900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9598600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9598900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9598980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9599680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9599980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9600060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9600760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9601060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9601140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9602860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9603700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9604000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9604080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9604780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9605620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9605920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9606000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9606700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9607540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9607840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9607920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9608620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9609460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9609760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9609840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9611560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9612400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9612915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9612980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9613720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9614560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9615075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9615140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9615880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9616720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9617235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9617300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9618040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9618880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9619395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9619460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9619905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9620235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9620565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9620895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9621225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9621555000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9621885000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9624105000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9624735000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9625060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9625665000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9626295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9626620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9627225000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9627855000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9628180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9628935000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9629535000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9629860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9631005000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9631635000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9631960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9633105000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9633735000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9634060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9635805000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9636435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9636760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9638505000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9639135000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9639460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9640545000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9640880000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9643005000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9643635000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9643960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9658820000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9670760000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9696220000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9699020000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9699915000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9713720000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9726260000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9727605000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9728805000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9729260000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9729615000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9729975000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9730845000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9731625000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9732405000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9734120000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9734475000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9735345000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9736125000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9737505000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9737715000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9737925000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9738135000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9738345000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9738555000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9738765000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9738975000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9739185000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9739395000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9739605000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9739815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9740025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9740595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9740920000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9745365000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9749085000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9751140000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9757040000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9760110000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9794475000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9795000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9795435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9795960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9797265000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9797895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9798465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9799155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9799845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9801380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9801380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9801380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9801380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9802020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9803320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9803320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9803320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9803320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9803960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9806220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9806220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9806220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9806220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9806860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9807585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9808220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9808860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9810075000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9810700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9812805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9813340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9813765000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9814300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9815595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9816225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9816795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9817485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9818145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9819700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9819700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9819700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9819700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9820340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9821620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9821620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9821620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9821620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9822260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9824520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9824520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9824520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9824520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9825160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9825885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9826520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9827160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9828375000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9829000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9831105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9831640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9832065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9832600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9833895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9834525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9835095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9835785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9836445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9838000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9838000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9838000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9838000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9838640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9839920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9839920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9839920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9839920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9840560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9842820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9842820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9842820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9842820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9843460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9844185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9844820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9845460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9846675000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9847300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9849220000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9849380000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9849620000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9850960000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9851120000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9851240000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9851360000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9851900000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9852080000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9852220000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9852360000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9855435000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9855840000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9855920000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9856260000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9857685000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9859060000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9859960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9860280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9864380000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9864720000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9866260000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9866580000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9868260000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9868600000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9870645000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9870945000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9871420000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9871740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9872080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9872400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9873525000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9873880000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9874540000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9874860000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9877035000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9877380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9878040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9878120000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9879060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9880020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9881000000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9881340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9881680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9882280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9883040000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9883380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9884600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9885800000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9886140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9887360000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9888075000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9888420000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9889080000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9889420000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9890260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9894255000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9894660000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9895425000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9895840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9896505000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9897000000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9898120000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9898280000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9898620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9899220000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9899660000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9900280000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9900440000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9900780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9901380000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9902500000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9902820000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9903160000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9903945000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9904300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9904965000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9905295000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9905640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9906195000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9906380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9906720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9907320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9907907000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9908100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9908440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9909040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9909705000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9909900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9910240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9910840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9911385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9911580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9911920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9912520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9913065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9913260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9913600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9914200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9914985000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9915180000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9915520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9916120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9916785000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9917115000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9917460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9918015000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9918200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9918540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9919095000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9919280000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9919620000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9920220000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9922035000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9922220000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9922560000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9923160000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9924075000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9924260000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9924600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9925200000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9928935000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9929145000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9929355000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9929895000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9930135000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9930345000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9930945000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9931155000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9931755000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9932385000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9932685000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9933405000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9933615000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9934395000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9939765000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9940005000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9940335000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9940665000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9946005000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9964800000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9965760000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9970060000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9970800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9971440000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9972480000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9973780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9974420000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9980500000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9981280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9982060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9983235000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9985980000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9986880000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9987840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9988680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 9989280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10023585000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10024080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10024545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10025040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10026375000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10027035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10027755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10028415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10029105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10030740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10030740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10030740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10030740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10031380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10032820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10032820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10032820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10032820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10033460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10035860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10035860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10035860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10035860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10036660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10037385000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10038020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10038660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10039875000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10040500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10042635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10043140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10043595000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10044100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10045425000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10046085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10046805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10047495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10048155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10049820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10049820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10049820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10049820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10050460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10051900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10051900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10051900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10051900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10052540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10054940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10054940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10054940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10054940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10055740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10056465000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10057100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10057740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10058955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10059580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10061715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10062220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10062675000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10063180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10064505000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10065165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10065885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10066575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10067235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10068900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10068900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10068900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10068900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10069540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10070980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10070980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10070980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10070980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10071620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10074020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10074020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10074020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10074020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10074820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10075545000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10076180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10076820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10078035000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10078660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10080580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10080740000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10080980000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10082320000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10082480000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10082600000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10082720000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10083260000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10083440000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10083580000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10083720000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10086795000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10087200000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10087280000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10087620000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10089045000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10090420000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10091320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10091640000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10095740000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10096080000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10097620000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10097940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10099620000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10099960000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10102035000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10102365000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10102940000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10103280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10103620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10103940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10105095000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10105440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10106100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10106440000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10108665000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10109020000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10109680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10109760000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10110700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10111620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10112600000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10112940000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10113280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10113880000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10114640000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10114980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10116340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10117540000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10117860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10119220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10119945000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10120300000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10120960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10121280000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10122120000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10126155000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10126560000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10127355000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10127760000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10128465000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10128960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10130080000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10130240000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10130580000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10131180000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10131620000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10132240000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10132400000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10132740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10133340000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10134460000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10134780000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10135120000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10135935000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10136280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10136955000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10137285000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10137640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10138185000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10138380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10138720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10139320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10139927000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10140120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10140460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10141060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10141725000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10141920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10142260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10142860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10143405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10143600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10143940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10144540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10145085000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10145280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10145620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10146220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10147035000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10147220000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10147560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10148160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10148835000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10149165000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10149520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10150065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10150260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10150600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10151175000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10151360000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10151700000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10152300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10154115000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10154300000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10154640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10155240000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10156155000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10156340000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10156680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10157280000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10161225000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10161465000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10161705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10162275000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10162545000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10162785000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10163415000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10163655000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10164285000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10164945000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10165275000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10166025000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10166265000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10167075000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10172475000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10172745000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10173105000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10173465000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10178835000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10197620000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10198580000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10202880000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10203740000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10204540000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10205580000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10207020000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10207660000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10214000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10214900000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10215800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10216995000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10219880000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10220780000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10221720000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10222560000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10223160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10257735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10258360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10258845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10259480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10260825000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10261515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10262235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10262925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10263585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10265220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10265220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10265220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10265220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10266020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10267440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10267440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10267440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10267440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10268240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10270640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10270640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10270640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10270640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10271440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10272165000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10272800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10273440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10274655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10275280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10277445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10278080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10278555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10279200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10280565000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10281255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10281975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10282665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10283325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10284960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10284960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10284960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10284960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10285760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10287180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10287180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10287180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10287180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10287980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10290380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10290380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10290380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10290380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10291180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10291905000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10292540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10293180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10294395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10295020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10297185000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10297820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10298295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10298940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10300305000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10300995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10301715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10302405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10303065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10304700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10304700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10304700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10304700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10305500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10306920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10306920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10306920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10306920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10307720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10310120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10310120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10310120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10310120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10310920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10311645000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10312280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10312920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10314135000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10314760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10316680000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10316840000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10317080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10318420000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10318580000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10318700000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10318820000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10319360000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10319540000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10319680000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10319820000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10322895000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10323300000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10323380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10323720000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10325145000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10326520000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10327420000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10327740000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10331980000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10332300000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10333840000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10334160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10335840000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10336180000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10338285000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10338645000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10339160000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10339500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10339840000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10340160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10341345000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10341700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10342360000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10342680000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10344975000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10345320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10345980000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10346060000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10347000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10347960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10348940000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10349280000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10349620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10350220000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10350980000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10351320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10352680000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10353880000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10354200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10355560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10356285000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10356640000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10357300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10357620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10358460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10362525000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10362940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10363755000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10364160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10364895000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10365400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10366520000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10366700000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10367040000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10367640000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10368080000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10368700000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10368860000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10369200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10369800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10370920000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10371240000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10371580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10372425000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10372780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10373445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10373775000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10374120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10374675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10374860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10375200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10375800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10376447000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10376640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10376980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10377580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10378245000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10378440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10378780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10379380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10379925000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10380120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10380460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10381060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10381605000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10381800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10382140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10382740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10383585000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10383780000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10384120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10384720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10385385000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10385715000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10386060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10386615000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10386800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10387140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10387755000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10387940000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10388280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10388880000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10390695000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10390880000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10391220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10391820000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10392735000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10392920000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10393260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10393860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10397835000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10398105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10398375000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10398975000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10399275000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10399545000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10400205000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10400475000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10401135000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10401825000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10402185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10402965000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10403235000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10404075000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10409505000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10409805000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10410195000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10410585000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10415985000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10434900000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10436020000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10440480000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10441340000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10442140000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10443180000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10444620000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10445420000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10451760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10452680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10453580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10454805000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10457840000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10458740000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10459680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10460520000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10461120000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10496805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10497400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10497915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10498520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10499895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10500615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10501335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10501995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10502685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10504260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10504260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10504260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10504260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10505060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10506480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10506480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10506480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10506480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10507280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10509680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10509680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10509680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10509680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10510480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10511205000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10511840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10512480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10513695000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10514320000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10516515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10517120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10517625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10518240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10519635000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10520355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10521075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10521735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10522425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10524000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10524000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10524000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10524000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10524800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10526220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10526220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10526220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10526220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10527020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10529420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10529420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10529420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10529420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10530220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10530945000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10531580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10532220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10533435000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10534060000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10536255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10536860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10537365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10537980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10539375000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10540095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10540815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10541475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10542165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10543740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10543740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10543740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10543740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10544540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10545960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10545960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10545960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10545960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10546760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10549160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10549160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10549160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10549160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10549960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10550685000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10551320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10551960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10553175000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10553800000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10555720000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10555880000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10556120000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10557460000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10557620000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10557740000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10557860000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10558400000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10558580000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10558720000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10558860000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10562115000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10562520000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10562600000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10562940000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10564365000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10565740000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10566640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10566960000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10571560000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10571880000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10573760000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10574100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10575960000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10576300000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10578615000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10579005000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10579620000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10579960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10580280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10580620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10581825000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10582180000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10582840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10583160000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10585515000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10585860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10586520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10586600000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10587540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10588500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10589640000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10589980000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10590300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10590900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10591800000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10592140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10593500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10594840000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10595160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10596520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10597245000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10597600000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10598260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10598580000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10599420000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10603875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10604280000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10605135000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10605540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10606305000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10606800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10608080000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10608260000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10608600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10609200000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10609640000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10610420000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10610600000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10610940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10611540000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10612820000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10613160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10613500000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10614375000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10614720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10615395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10615725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10616080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10616625000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10616820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10617160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10617760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10618427000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10618620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10618960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10619560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10620225000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10620420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10620760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10621360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10621905000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10622100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10622440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10623040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10623585000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10623780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10624120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10624720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10625595000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10625780000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10626120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10626720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10627395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10627725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10628080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10628625000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10628820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10629160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10629795000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10629980000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10630320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10630920000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10632735000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10632920000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10633260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10633860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10634775000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10634960000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10635300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10635900000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10639905000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10640205000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10640505000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10641135000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10641465000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10641765000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10642455000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10642755000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10643445000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10644165000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10644555000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10645365000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10645665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10646535000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10651995000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10652325000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10652745000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10653165000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10658595000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10677500000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10678620000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10683200000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10684060000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10684860000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10685900000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10687320000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10688120000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10694460000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10695380000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10696280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10697535000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10700560000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10701460000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10702420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10703260000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10703860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10706600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10707495000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10707840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10708960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10709655000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10710000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10711240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10712445000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10712800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10720520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10732245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10732600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10733360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10733700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10734120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10734960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10735300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10735620000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10735960000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10736360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10736835000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10736900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10737880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10738200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10738620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10740120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10740460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10740780000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10741120000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10741520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10741995000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10742060000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10744980000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10747710000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10749780000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10752510000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10754400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10754740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10754820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10755480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10755820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10755900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10756560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10756900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10756980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10757640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10757980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10758060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10759800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10760140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10760220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10760880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10761220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10761300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10761960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10762300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10762380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10763040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10763380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10763460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10765200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10766140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10766460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10766540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10767240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10768180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10768500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10768580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10769280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10770220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10770540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10770620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10771320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10772260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10772580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10772660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10774440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10775380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10775955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10776020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10776720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10777660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10778235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10778300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10779000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10779940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10780515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10780580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10781280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10782220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10782795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10782860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10783305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10783635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10783965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10784295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10784625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10784955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10785285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10787360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10788255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10788600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10789720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10790415000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10790760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10792000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10793205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10793560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10801280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10813005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10813360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10814120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10814460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10814880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10815720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10816060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10816380000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10816720000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10817120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10817595000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10817660000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10818640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10818960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10819380000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10820880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10821220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10821540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10821880000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10822280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10822755000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10822820000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10825740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10828470000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10830540000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10833270000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10835160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10835500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10835580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10836240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10836580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10836660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10837320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10837660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10837740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10838400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10838740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10838820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10840560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10840900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10840980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10841640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10841980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10842060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10842720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10843060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10843140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10843800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10844140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10844220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10845960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10846900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10847220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10847300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10848000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10848940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10849260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10849340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10850040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10850980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10851300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10851380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10852080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10853020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10853340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10853420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10855200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10856140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10856715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10856780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10857480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10858420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10858995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10859060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10859760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10860700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10861275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10861340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10862040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10862980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10863555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10863620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10864065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10864395000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10864725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10865055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10865385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10865715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10866045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10868120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10869015000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10869360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10870480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10871175000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10871520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10872760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10873965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10874320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10882040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10893765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10894120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10894880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10895220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10895640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10896480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10896820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10897140000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10897480000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10897880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10898355000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10898420000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10899400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10899720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10900140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10901640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10901980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10902300000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10902640000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10903040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10903515000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10903580000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10906500000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10909230000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10911300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10914030000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10915920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10916260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10916340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10917000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10917340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10917420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10918080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10918420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10918500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10919160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10919500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10919580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10921320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10921660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10921740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10922400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10922740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10922820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10923480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10923820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10923900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10924560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10924900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10924980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10926720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10927660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10927980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10928060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10928760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10929700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10930020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10930100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10930800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10931740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10932060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10932140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10932840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10933780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10934100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10934180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10935960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10936900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10937475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10937540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10938240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10939180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10939755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10939820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10940520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10941460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10942035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10942100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10942800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10943740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10944315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10944380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10944825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10945155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10945485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10945815000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10946145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10946475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10946805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10948880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10949775000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10950120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10951240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10951935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10952280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10953520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10954725000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10955080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10962800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10974525000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10974880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10975640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10975980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10976400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10977240000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10977580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10977900000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10978240000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10978640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10979115000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10979180000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10980160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10980480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10980900000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10982400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10982740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10983060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10983400000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10983800000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10984275000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10984340000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10987260000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10989990000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10992060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10994790000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10996680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10997020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10997100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10997760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10998100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10998180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10998840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10999180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10999260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 10999920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11000260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11000340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11002080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11002420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11002500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11003160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11003500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11003580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11004240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11004580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11004660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11005320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11005660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11005740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11007480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11008420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11008740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11008820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11009520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11010460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11010780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11010860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11011560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11012500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11012820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11012900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11013600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11014540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11014860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11014940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11016720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11017660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11018235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11018300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11019000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11019940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11020515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11020580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11021280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11022220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11022795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11022860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11023560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11024500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11025075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11025140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11025585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11025915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11026245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11026575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11026905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11027235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11027565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11029935000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11030595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11030940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11031495000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11032155000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11032500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11033055000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11033715000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11034060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11034675000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11035335000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11035680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11036535000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11037195000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11037540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11038395000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11039055000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11039400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11040585000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11041275000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11041620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11042805000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11043495000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11043840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11044635000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11044980000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11047245000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11047935000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11048280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11057900000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11064520000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11078620000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11081640000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11082465000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11090900000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11097880000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11098875000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11099745000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11100165000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11100495000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11100825000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11101605000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11102295000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11102985000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11104845000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11105175000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11105955000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11106645000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11108175000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11108385000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11108595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11108805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11109015000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11109225000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11109435000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11109645000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11109855000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11110065000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11110275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11110485000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11110695000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11111295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11111640000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11116455000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11119905000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11121520000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11127440000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11130390000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11166075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11166540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11166975000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11167440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11168685000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11169345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11169975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11170605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11171205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11172700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11172700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11172700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11172700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11173420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11174740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11174740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11174740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11174740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11175460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11177420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11177420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11177420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11177420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11178140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11178885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11179600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11180320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11181555000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11182260000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11184375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11184840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11185275000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11185740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11186985000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11187645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11188275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11188905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11189505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11191000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11191000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11191000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11191000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11191720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11193040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11193040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11193040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11193040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11193760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11195720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11195720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11195720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11195720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11196440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11197185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11197900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11198620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11199855000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11200560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11202675000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11203140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11203575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11204040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11205285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11205945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11206575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11207205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11207805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11209300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11209300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11209300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11209300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11210020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11211340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11211340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11211340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11211340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11212060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11214020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11214020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11214020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11214020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11214740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11215485000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11216200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11216920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11218155000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11218860000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11220840000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11221020000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11221260000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11222760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11222940000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11223060000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11223180000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11223780000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11223980000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11224120000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11224260000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11227425000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11227820000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11227900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11228240000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11229735000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11231240000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11232200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11232540000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11236840000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11237180000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11238900000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11239260000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11241100000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11241440000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11243655000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11243955000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11244560000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11244920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11245280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11245640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11246835000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11247200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11247920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11248280000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11250435000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11250800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11251520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11251600000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11252580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11253560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11254640000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11255000000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11255360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11256000000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11256700000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11257040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11258260000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11259480000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11259840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11261040000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11261775000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11262140000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11262860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11263220000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11264120000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11268345000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11268780000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11269545000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11269980000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11270655000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11271180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11272380000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11272560000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11272920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11273540000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11274000000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11274700000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11274860000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11275220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11275860000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11277060000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11277420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11277780000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11278575000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11278940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11279625000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11279955000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11280320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11280885000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11281080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11281440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11282060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11282657000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11282840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11283200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11283840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11284515000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11284700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11285060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11285700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11286255000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11286440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11286800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11287440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11287995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11288180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11288540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11289180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11289975000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11290160000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11290520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11291160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11291835000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11292165000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11292540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11293095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11293280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11293640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11294205000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11294400000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11294760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11295380000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11297235000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11297420000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11297780000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11298420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11299395000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11299580000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11299940000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11300580000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11304435000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11304645000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11304855000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11305425000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11305665000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11305875000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11306475000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11306685000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11307285000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11307945000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11308215000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11308935000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11309145000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11309895000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11316525000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11316765000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11317065000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11317365000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11320995000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11337900000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11338800000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11342980000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11343740000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11344460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11345320000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11346640000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11347360000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11353080000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11353920000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11354760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11356005000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11358380000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11359240000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11360220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11361060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11361660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11397285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11397900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11398365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11398980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11400255000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11400915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11401545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11402175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11402775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11404240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11404240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11404240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11404240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11404960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11406280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11406280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11406280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11406280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11407000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11409120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11409120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11409120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11409120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11409840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11410575000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11411280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11412000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11413215000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11413920000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11416065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11416680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11417145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11417760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11419035000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11419695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11420325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11420955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11421555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11423020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11423020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11423020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11423020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11423740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11425060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11425060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11425060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11425060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11425780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11427900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11427900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11427900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11427900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11428620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11429355000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11430060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11430780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11431995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11432700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11434845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11435460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11435925000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11436540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11437815000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11438475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11439105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11439735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11440335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11441800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11441800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11441800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11441800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11442520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11443840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11443840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11443840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11443840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11444560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11446680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11446680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11446680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11446680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11447400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11448135000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11448840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11449560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11450775000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11451480000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11453460000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11453640000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11453880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11455380000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11455560000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11455680000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11455800000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11456400000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11456600000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11456740000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11456880000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11460045000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11460440000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11460520000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11460860000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11462355000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11463860000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11464820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11465160000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11469620000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11469980000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11471700000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11472060000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11473900000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11474240000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11476485000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11476815000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11477360000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11477720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11478080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11478440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11479665000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11480040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11480760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11481120000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11483295000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11483660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11484380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11484460000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11485440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11486420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11487500000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11487860000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11488220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11488860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11489720000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11490080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11491300000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11492520000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11492880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11494080000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11494815000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11495180000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11495900000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11496260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11497160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11501415000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11501840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11502645000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11503080000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11503785000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11504300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11505540000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11505720000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11506080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11506700000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11507160000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11507860000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11508020000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11508380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11509020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11510220000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11510580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11510940000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11511765000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11512140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11512815000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11513145000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11513520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11514075000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11514260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11514620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11515260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11515877000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11516060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11516420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11517060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11517735000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11517920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11518280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11518920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11519475000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11519660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11520020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11520660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11521215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11521400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11521760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11522400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11523225000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11523420000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11523780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11524400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11525085000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11525415000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11525780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11526345000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11526540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11526900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11527485000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11527680000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11528040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11528660000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11530515000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11530700000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11531060000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11531700000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11532675000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11532860000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11533220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11533860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11537745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11537985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11538225000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11538825000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11539095000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11539335000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11539965000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11540205000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11540835000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11541525000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11541825000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11542575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11542815000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11543595000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11550255000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11550525000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11550855000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11551185000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11554845000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11571760000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11572840000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11577020000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11577900000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11578620000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11579480000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11580800000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11581520000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11587260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11588100000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11588940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11590215000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11592740000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11593600000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11594580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11595420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11596020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11631915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11632500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11632995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11633580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11634885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11635605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11636235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11637015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11637795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11639540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11639540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11639540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11639540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11640260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11641740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11641740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11641740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11641740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11642460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11644560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11644560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11644560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11644560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11645280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11646015000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11646720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11647440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11648655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11649360000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11651535000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11652120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11652615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11653200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11654505000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11655225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11655855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11656635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11657415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11659160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11659160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11659160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11659160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11659880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11661360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11661360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11661360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11661360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11662080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11664180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11664180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11664180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11664180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11664900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11665635000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11666340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11667060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11668275000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11668980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11671155000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11671740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11672235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11672820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11674125000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11674845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11675475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11676255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11677035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11678780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11678780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11678780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11678780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11679500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11680980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11680980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11680980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11680980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11681700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11683800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11683800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11683800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11683800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11684520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11685255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11685960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11686680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11687895000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11688600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11690580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11690760000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11691000000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11692500000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11692680000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11692800000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11692920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11693520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11693720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11693860000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11694000000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11697165000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11697560000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11697640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11697980000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11699475000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11700980000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11701940000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11702280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11706740000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11707100000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11708820000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11709180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11711020000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11711360000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11713635000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11713995000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11714660000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11715020000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11715380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11715740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11716995000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11717360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11718080000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11718440000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11720715000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11721080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11721800000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11721880000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11722860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11723840000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11724920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11725280000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11725640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11726280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11727140000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11727500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11728880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11730100000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11730440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11731820000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11732565000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11732940000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11733660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11734020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11734880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11739165000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11739600000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11740425000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11740860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11741595000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11742120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11743320000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11743500000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11743860000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11744480000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11744940000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11745640000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11745800000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11746160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11746800000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11748000000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11748360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11748720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11749575000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11749940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11750625000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11750955000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11751320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11751885000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11752080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11752440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11753060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11753717000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11753900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11754260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11754900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11755575000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11755760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11756120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11756760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11757315000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11757500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11757860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11758500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11759055000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11759240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11759600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11760240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11761095000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11761280000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11761640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11762280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11762955000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11763285000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11763660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11764215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11764400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11764760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11765385000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11765580000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11765940000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11766560000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11768415000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11768600000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11768960000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11769600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11770575000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11770760000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11771120000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11771760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11775675000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11775945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11776215000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11776845000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11777145000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11777415000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11778075000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11778345000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11779005000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11779725000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11780055000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11780835000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11781105000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11781915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11788605000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11788905000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11789265000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11789625000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11793315000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11812800000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11813880000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11818060000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11818940000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11819660000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11820680000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11822160000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11822880000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11828580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11829420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11830260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11831565000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11834100000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11834960000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11835940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11836800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11837400000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11873325000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11873880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11874405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11874960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11876295000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11877015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11877795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11878575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11879355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11881100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11881100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11881100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11881100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11882000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11883480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11883480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11883480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11883480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11884200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11886300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11886300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11886300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11886300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11887200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11887935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11888640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11889360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11890575000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11891280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11893485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11894040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11894565000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11895120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11896455000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11897175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11897955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11898735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11899515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11901260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11901260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11901260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11901260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11902160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11903640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11903640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11903640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11903640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11904360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11906460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11906460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11906460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11906460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11907360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11908095000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11908800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11909520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11910735000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11911440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11913645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11914200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11914725000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11915280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11916615000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11917335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11918115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11918895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11919675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11921420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11921420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11921420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11921420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11922320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11923800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11923800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11923800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11923800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11924520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11926620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11926620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11926620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11926620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11927520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11928255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11928960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11929680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11930895000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11931600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11933580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11933760000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11934000000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11935500000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11935680000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11935800000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11935920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11936520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11936720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11936860000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11937000000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11940165000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11940560000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11940640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11940980000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11942475000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11943980000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11944940000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11945280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11949740000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11950100000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11951820000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11952180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11954020000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11954360000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11956665000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11957055000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11957660000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11958020000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11958380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11958740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11960025000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11960400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11961120000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11961480000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11963775000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11964140000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11964860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11964940000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11965920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11966900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11967980000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11968340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11968700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11969340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11970200000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11970560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11971940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11973160000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11973500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11974880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11975625000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11976000000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11976720000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11977080000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11977940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11982255000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11982680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11983545000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11983980000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11984745000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11985260000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11986500000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11986680000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11987040000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11987660000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11988120000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11988820000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11988980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11989340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11989980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11991180000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11991540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11991900000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11992785000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11993160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11993835000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11994165000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11994540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11995095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11995280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11995640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11996280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11996957000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11997140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11997500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11998140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11998815000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11999000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 11999360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12000000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12000555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12000740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12001100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12001740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12002295000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12002480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12002840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12003480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12004365000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12004560000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12004920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12005540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12006225000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12006555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12006920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12007485000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12007680000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12008040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12008685000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12008880000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12009240000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12009860000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12011715000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12011900000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12012260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12012900000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12013875000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12014060000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12014420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12015060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12019185000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12019485000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12019785000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12020445000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12020775000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12021075000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12021765000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12022065000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12022755000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12023505000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12023865000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12024675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12024975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12025815000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12032535000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12032865000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12033255000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12033645000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12037365000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12056860000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12057940000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12062420000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12063300000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12064020000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12065040000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12066500000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12067400000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12073420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12074440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12075460000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12076815000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12079500000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12080360000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12081340000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12082200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12082800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12085740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12086775000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12087140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12088400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12089325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12089700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12091060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12092505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12092880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12102500000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12116505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12116880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12117720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12118080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12118520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12119400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12119760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12120120000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12120480000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12120920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12121395000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12121460000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12122560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12122900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12123340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12125100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12125460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12125820000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12126180000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12126620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12127095000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12127160000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12130400000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12133320000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12135720000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12138630000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12140660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12141020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12141100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12141860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12142220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12142300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12143060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12143420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12143500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12144260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12144620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12144700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12146600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12146960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12147040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12147800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12148160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12148240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12149000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12149360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12149440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12150200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12150560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12150640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12152540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12153540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12153900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12153980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12154760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12155760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12156120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12156200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12156980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12157980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12158340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12158420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12159200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12160200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12160560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12160640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12162560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12163560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12164175000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12164240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12165020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12166020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12166635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12166700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12167480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12168480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12169095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12169160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12169940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12170940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12171555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12171620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12172065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12172395000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12172725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12173055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12173385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12173715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12174045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12176220000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12177255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12177620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12178880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12179805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12180180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12181540000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12182985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12183360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12192980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12206985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12207360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12208200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12208560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12209000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12209880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12210240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12210600000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12210960000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12211400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12211875000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12211940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12213040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12213380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12213820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12215580000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12215940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12216300000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12216660000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12217100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12217575000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12217640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12220880000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12223800000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12226200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12229110000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12231140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12231500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12231580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12232340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12232700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12232780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12233540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12233900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12233980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12234740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12235100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12235180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12237080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12237440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12237520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12238280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12238640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12238720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12239480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12239840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12239920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12240680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12241040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12241120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12243020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12244020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12244380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12244460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12245240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12246240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12246600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12246680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12247460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12248460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12248820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12248900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12249680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12250680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12251040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12251120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12253040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12254040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12254655000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12254720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12255500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12256500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12257115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12257180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12257960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12258960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12259575000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12259640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12260420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12261420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12262035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12262100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12262545000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12262875000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12263205000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12263535000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12263865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12264195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12264525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12266700000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12267735000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12268100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12269360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12270285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12270660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12272020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12273465000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12273840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12283460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12297465000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12297840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12298680000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12299040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12299480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12300360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12300720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12301080000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12301440000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12301880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12302355000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12302420000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12303520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12303860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12304300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12306060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12306420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12306780000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12307140000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12307580000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12308055000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12308120000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12311360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12314280000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12316680000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12319590000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12321620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12321980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12322060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12322820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12323180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12323260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12324020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12324380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12324460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12325220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12325580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12325660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12327560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12327920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12328000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12328760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12329120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12329200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12329960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12330320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12330400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12331160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12331520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12331600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12333500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12334500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12334860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12334940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12335720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12336720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12337080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12337160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12337940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12338940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12339300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12339380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12340160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12341160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12341520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12341600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12343520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12344520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12345135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12345200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12345980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12346980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12347595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12347660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12348440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12349440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12350055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12350120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12350900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12351900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12352515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12352580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12353025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12353355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12353685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12354015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12354345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12354675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12355005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12357180000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12358215000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12358580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12359840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12360765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12361140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12362500000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12363945000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12364320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12373940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12387945000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12388320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12389160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12389520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12389960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12390840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12391200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12391560000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12391920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12392360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12392835000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12392900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12394000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12394340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12394780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12396540000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12396900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12397260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12397620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12398060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12398535000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12398600000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12401840000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12404760000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12407160000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12410070000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12412100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12412460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12412540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12413300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12413660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12413740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12414500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12414860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12414940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12415700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12416060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12416140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12418040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12418400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12418480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12419240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12419600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12419680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12420440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12420800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12420880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12421640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12422000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12422080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12423980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12424980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12425340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12425420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12426200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12427200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12427560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12427640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12428420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12429420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12429780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12429860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12430640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12431640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12432000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12432080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12434000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12435000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12435615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12435680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12436460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12437460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12438075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12438140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12438920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12439920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12440535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12440600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12441380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12442380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12442995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12443060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12443505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12443835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12444165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12444495000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12444825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12445155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12445485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12447945000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12448665000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12449040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12449655000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12450345000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12450720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12451335000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12452025000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12452400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12453135000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12453825000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12454200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12455235000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12455925000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12456300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12457335000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12458025000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12458400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12459855000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12460545000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12460920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12462375000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12463065000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12463440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12464415000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12464780000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12467145000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12467865000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12468240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12479860000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12488360000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12506500000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12509760000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12510645000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12521000000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12529880000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12531045000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12532065000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12532520000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12532860000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12533180000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12533985000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12534705000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12535425000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12537360000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12537680000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12538485000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12539205000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12540765000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12540975000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12541185000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12541395000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12541605000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12541815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12542025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12542235000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12542445000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12542655000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12542865000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12543075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12543285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12543915000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12544280000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12549135000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12552615000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12554360000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12560240000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12563310000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12600915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12601480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12601905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12602480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12603675000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12604335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12605055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12605745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12606435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12607980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12607980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12607980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12607980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12608780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12610080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12610080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12610080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12610080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12610880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12612540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12612540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12612540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12612540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12613340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12614115000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12614900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12615700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12616995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12617780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12620115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12620680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12621105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12621680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12622875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12623535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12624255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12624945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12625635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12627180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12627180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12627180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12627180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12627980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12629280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12629280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12629280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12629280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12630080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12631740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12631740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12631740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12631740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12632540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12633315000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12634100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12634900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12636195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12636980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12639315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12639880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12640305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12640880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12642075000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12642735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12643455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12644145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12644835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12646380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12646380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12646380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12646380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12647180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12648480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12648480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12648480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12648480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12649280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12650940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12650940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12650940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12650940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12651740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12652515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12653300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12654100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12655395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12656180000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12658420000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12658620000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12658860000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12660540000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12660740000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12660860000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12660980000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12661640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12661860000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12662000000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12662140000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12665595000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12666040000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12666120000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12666500000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12668085000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12669580000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12670580000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12670940000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12675540000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12675920000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12677820000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12678200000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12680240000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12680620000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12682965000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12683265000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12683820000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12684200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12684580000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12684940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12686205000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12686600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12687340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12687700000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12689895000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12690280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12691000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12691080000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12692140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12693160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12694320000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12694700000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12695080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12695740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12696520000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12696880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12698040000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12699240000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12699620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12700800000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12701565000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12701960000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12702700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12703060000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12704000000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12708615000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12709060000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12709845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12710300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12711015000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12711560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12712920000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12713100000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12713480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12714160000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12714620000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12715400000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12715580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12715960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12716620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12717960000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12718340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12718720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12719565000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12719960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12720675000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12721005000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12721400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12721995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12722180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12722560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12723220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12723827000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12724020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12724400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12725080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12725775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12725960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12726340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12727000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12727575000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12727760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12728140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12728800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12729375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12729560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12729940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12730600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12731445000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12731640000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12732020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12732700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12733395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12733725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12734120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12734715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12734900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12735280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12735855000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12736040000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12736420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12737080000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12739065000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12739260000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12739640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12740320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12741255000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12741440000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12741820000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12742480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12746715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12746925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12747135000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12747705000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12747945000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12748155000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12748725000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12748935000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12749505000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12750225000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12750465000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12751215000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12751425000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12752175000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12760035000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12760275000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12760545000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12760815000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12762735000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12779280000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12780280000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12784380000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12785160000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12785960000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12786740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12788040000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12788840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12793960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12794880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12795820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12797145000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12799120000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12799900000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12800880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12801760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12802360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12839865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12840400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12840855000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12841400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12842625000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12843315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12844005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12844725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12845415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12846940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12846940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12846940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12846940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12847740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12849040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12849040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12849040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12849040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12849840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12851500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12851500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12851500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12851500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12852300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12853065000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12853860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12854660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12855975000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12856760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12859125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12859660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12860115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12860660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12861885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12862575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12863265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12863985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12864675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12866200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12866200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12866200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12866200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12867000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12868300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12868300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12868300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12868300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12869100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12870760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12870760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12870760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12870760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12871560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12872325000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12873120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12873920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12875235000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12876020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12878385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12878920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12879375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12879920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12881145000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12881835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12882525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12883245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12883935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12885460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12885460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12885460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12885460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12886260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12887560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12887560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12887560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12887560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12888360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12890020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12890020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12890020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12890020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12890820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12891585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12892380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12893180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12894495000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12895280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12897520000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12897720000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12897960000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12899640000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12899840000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12899960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12900080000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12900740000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12900960000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12901100000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12901240000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12904695000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12905140000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12905220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12905600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12907185000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12908680000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12909680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12910040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12914640000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12915020000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12916920000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12917300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12919340000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12919720000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12922095000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12922425000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12923120000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12923500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12923860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12924220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12925515000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12925900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12926620000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12926980000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12929205000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12929600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12930340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12930420000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12931480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12932500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12933660000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12934040000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12934420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12935080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12935860000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12936220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12937380000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12938580000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12938960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12940140000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12940905000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12941300000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12942040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12942400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12943340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12947985000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12948440000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12949275000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12949720000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12950445000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12950980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12952320000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12952500000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12952880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12953560000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12954020000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12954800000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12954980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12955360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12956020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12957360000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12957740000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12958120000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12958995000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12959380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12960075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12960405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12960800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12961395000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12961580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12961960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12962620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12963257000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12963440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12963820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12964480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12965175000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12965360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12965740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12966400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12966975000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12967160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12967540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12968200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12968775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12968960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12969340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12970000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12970875000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12971060000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12971440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12972100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12972795000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12973125000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12973520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12974115000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12974300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12974680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12975285000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12975480000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12975860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12976540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12978525000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12978720000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12979100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12979780000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12980715000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12980900000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12981280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12981940000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12986205000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12986445000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12986685000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12987315000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12987585000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12987825000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12988455000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12988695000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12989295000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12990015000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12990285000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12991065000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12991305000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12992085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 12999975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13000245000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13000545000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13000845000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13002795000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13020280000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13021280000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13025380000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13026160000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13026960000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13027740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13029040000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13029840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13035280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13036200000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13037140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13038495000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13040640000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13041420000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13042420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13043280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13043880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13081695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13082400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13082895000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13083600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13084845000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13085565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13086255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13086975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13087665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13089340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13089340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13089340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13089340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13090140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13091620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13091620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13091620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13091620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13092420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13094080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13094080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13094080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13094080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13094880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13095645000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13096440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13097240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13098555000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13099340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13101735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13102440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13102935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13103640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13104885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13105605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13106295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13107015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13107705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13109380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13109380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13109380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13109380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13110180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13111660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13111660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13111660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13111660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13112460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13114120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13114120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13114120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13114120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13114920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13115685000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13116480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13117280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13118595000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13119380000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13121775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13122480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13122975000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13123680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13124925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13125645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13126335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13127055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13127745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13129420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13129420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13129420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13129420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13130220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13131700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13131700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13131700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13131700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13132500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13134160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13134160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13134160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13134160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13134960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13135725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13136520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13137320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13138635000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13139420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13141660000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13141860000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13142100000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13143780000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13143980000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13144100000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13144220000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13144880000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13145100000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13145240000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13145380000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13148835000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13149280000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13149360000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13149740000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13151325000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13152820000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13153820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13154180000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13158780000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13159160000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13161060000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13161440000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13163480000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13163860000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13166265000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13166625000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13167260000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13167640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13168000000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13168360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13169685000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13170080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13170820000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13171180000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13173465000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13173860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13174600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13174680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13175740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13176760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13177920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13178300000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13178680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13179340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13180120000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13180480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13181820000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13183020000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13183400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13184760000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13185525000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13185920000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13186660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13187020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13187960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13192635000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13193080000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13193925000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13194380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13195155000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13195700000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13197060000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13197240000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13197620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13198300000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13198760000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13199540000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13199720000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13200100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13200760000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13202100000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13202480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13202860000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13203765000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13204160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13204875000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13205205000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13205600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13206195000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13206380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13206760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13207420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13208087000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13208280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13208660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13209340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13210035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13210220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13210600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13211260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13211835000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13212020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13212400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13213060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13213635000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13213820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13214200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13214860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13215765000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13215960000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13216340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13217020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13217715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13218045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13218440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13219035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13219220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13219600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13220235000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13220420000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13220800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13221460000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13223445000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13223640000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13224020000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13224700000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13225635000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13225820000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13226200000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13226860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13231155000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13231425000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13231695000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13232325000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13232625000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13232895000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13233525000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13233795000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13234425000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13235205000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13235505000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13236315000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13236585000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13237395000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13245315000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13245615000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13245945000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13246275000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13248255000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13267560000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13268760000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13272980000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13273880000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13274680000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13275640000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13277100000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13277900000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13283320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13284240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13285180000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13286565000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13288720000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13289680000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13290660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13291540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13292140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13329945000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13330620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13331145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13331820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13333095000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13333845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13334565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13335255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13335945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13337580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13337580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13337580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13337580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13338380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13339860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13339860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13339860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13339860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13340660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13342500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13342500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13342500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13342500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13343300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13344075000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13344860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13345660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13346955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13347740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13350165000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13350840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13351365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13352040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13353315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13354065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13354785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13355475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13356165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13357800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13357800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13357800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13357800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13358600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13360080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13360080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13360080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13360080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13360880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13362720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13362720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13362720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13362720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13363520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13364295000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13365080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13365880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13367175000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13367960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13370385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13371060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13371585000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13372260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13373535000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13374285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13375005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13375695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13376385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13378020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13378020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13378020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13378020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13378820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13380300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13380300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13380300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13380300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13381100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13382940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13382940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13382940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13382940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13383740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13384515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13385300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13386100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13387395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13388180000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13390420000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13390620000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13390860000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13392540000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13392740000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13392860000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13392980000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13393640000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13393860000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13394000000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13394140000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13397595000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13398040000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13398120000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13398500000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13400085000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13401580000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13402580000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13402940000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13407720000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13408100000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13410000000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13410380000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13412420000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13412800000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13415235000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13415625000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13416200000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13416580000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13416940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13417300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13418655000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13419040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13419760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13420120000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13422465000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13422860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13423600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13423680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13424740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13425760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13426920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13427300000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13427680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13428340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13429120000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13429480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13430820000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13432020000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13432400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13433760000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13434525000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13434920000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13435660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13436020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13436960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13441665000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13442120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13443015000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13443460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13444245000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13444780000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13446120000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13446300000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13446680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13447360000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13447820000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13448600000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13448780000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13449160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13449820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13451160000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13451540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13451920000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13452855000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13453240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13453935000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13454265000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13454660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13455255000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13455440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13455820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13456480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13457177000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13457360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13457740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13458400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13459095000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13459280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13459660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13460320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13460895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13461080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13461460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13462120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13462695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13462880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13463260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13463920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13464855000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13465040000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13465420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13466080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13466775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13467105000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13467500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13468095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13468280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13468660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13469325000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13469520000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13469900000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13470580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13472565000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13472760000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13473140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13473820000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13474755000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13474940000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13475320000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13475980000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13480305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13480605000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13480905000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13481595000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13481925000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13482225000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13482915000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13483215000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13483875000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13484655000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13484985000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13485825000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13486125000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13486965000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13494915000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13495245000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13495605000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13495965000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13497975000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13517320000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13518520000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13522940000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13523840000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13524640000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13525600000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13527060000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13527860000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13533280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13534200000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13535140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13536555000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13538880000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13539840000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13540840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13541700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13542300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13545440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13546155000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13546540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13547680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13548315000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13548700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13549900000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13550745000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13551140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13555300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13563885000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13564280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13565120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13565500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13565940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13566780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13567160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13567540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13567900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13568340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13568865000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13568940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13569840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13570220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13570680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13571820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13572200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13572580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13572940000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13573380000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13573905000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13573980000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13577100000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13579830000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13581960000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13584690000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13586740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13587100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13587180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13587880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13588240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13588320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13589020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13589380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13589460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13590160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13590520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13590600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13592560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13592920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13593000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13593700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13594060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13594140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13594840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13595200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13595280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13595980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13596340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13596420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13598380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13599400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13599760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13599840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13600540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13601560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13601920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13602000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13602700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13603720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13604080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13604160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13604860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13605880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13606240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13606320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13608280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13609300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13609935000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13610000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13610740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13611760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13612395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13612460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13613200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13614220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13614855000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13614920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13615660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13616680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13617315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13617380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13617825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13618155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13618485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13618815000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13619145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13619475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13619805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13622100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13622805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13623200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13624360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13624995000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13625380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13626580000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13627425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13627820000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13631980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13640565000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13640960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13641800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13642180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13642620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13643460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13643840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13644220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13644580000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13645020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13645545000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13645620000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13646520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13646900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13647360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13648500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13648880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13649260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13649620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13650060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13650585000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13650660000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13653780000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13656510000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13658640000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13661370000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13663420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13663780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13663860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13664560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13664920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13665000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13665700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13666060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13666140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13666840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13667200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13667280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13669240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13669600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13669680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13670380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13670740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13670820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13671520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13671880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13671960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13672660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13673020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13673100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13675060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13676080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13676440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13676520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13677220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13678240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13678600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13678680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13679380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13680400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13680760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13680840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13681540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13682560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13682920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13683000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13684960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13685980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13686615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13686680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13687420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13688440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13689075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13689140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13689880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13690900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13691535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13691600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13692340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13693360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13693995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13694060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13694505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13694835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13695165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13695495000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13695825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13696155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13696485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13698780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13699485000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13699880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13701040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13701675000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13702060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13703260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13704105000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13704500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13708660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13717245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13717640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13718480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13718860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13719300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13720140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13720520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13720900000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13721260000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13721700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13722225000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13722300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13723200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13723580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13724040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13725180000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13725560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13725940000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13726300000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13726740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13727265000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13727340000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13730460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13733190000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13735320000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13738050000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13740100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13740460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13740540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13741240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13741600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13741680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13742380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13742740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13742820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13743520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13743880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13743960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13745920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13746280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13746360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13747060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13747420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13747500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13748200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13748560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13748640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13749340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13749700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13749780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13751740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13752760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13753120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13753200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13753900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13754920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13755280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13755360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13756060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13757080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13757440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13757520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13758220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13759240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13759600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13759680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13761640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13762660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13763295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13763360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13764100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13765120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13765755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13765820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13766560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13767580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13768215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13768280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13769020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13770040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13770675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13770740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13771185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13771515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13771845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13772175000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13772505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13772835000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13773165000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13775460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13776165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13776560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13777720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13778355000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13778740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13779940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13780785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13781180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13785340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13793925000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13794320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13795160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13795540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13795980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13796820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13797200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13797580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13797940000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13798380000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13798905000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13798980000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13799880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13800260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13800720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13801860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13802240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13802620000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13802980000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13803420000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13803945000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13804020000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13807140000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13809870000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13812000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13814730000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13816780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13817140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13817220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13817920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13818280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13818360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13819060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13819420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13819500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13820200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13820560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13820640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13822600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13822960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13823040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13823740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13824100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13824180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13824880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13825240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13825320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13826020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13826380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13826460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13828420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13829440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13829800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13829880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13830580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13831600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13831960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13832040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13832740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13833760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13834120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13834200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13834900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13835920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13836280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13836360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13838320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13839340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13839975000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13840040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13840780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13841800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13842435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13842500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13843240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13844260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13844895000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13844960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13845700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13846720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13847355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13847420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13847865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13848195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13848525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13848855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13849185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13849515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13849845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13852425000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13853175000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13853560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13854105000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13854855000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13855240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13855785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13856535000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13856920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13857555000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13858275000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13858660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13859355000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13860075000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13860460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13861185000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13861935000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13862320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13863165000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13863915000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13864300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13865175000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13865895000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13866280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13866945000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13867340000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13869825000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13870575000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13870960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13877120000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13880320000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13887100000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13890360000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13891185000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13896140000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13899460000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13900275000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13900965000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13901360000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13901640000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13901900000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13902615000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13903245000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13903875000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13905900000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13906160000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13906875000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13907505000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13909185000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13909395000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13909605000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13909815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13910025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13910235000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13910445000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13910655000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13910865000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13911075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13911285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13911495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13911705000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13912395000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13912780000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13917945000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13921125000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13922460000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13928360000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13931310000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13964205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13964640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13965045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13965480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13966875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13967475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13968015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13968615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13969185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13970720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13970720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13970720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13970720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13971280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13972640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13972640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13972640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13972640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13973200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13976160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13976160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13976160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13976160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13976860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13977555000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13978240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13978800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13979955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13980640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13982505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13982940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13983345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13983780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13985175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13985775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13986315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13986915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13987485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13989020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13989020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13989020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13989020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13989580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13990940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13990940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13990940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13990940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13991500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13994460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13994460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13994460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13994460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13995160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13995855000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13996540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13997100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13998255000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 13998940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14000805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14001240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14001645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14002080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14003475000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14004075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14004615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14005215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14005785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14007320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14007320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14007320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14007320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14007880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14009240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14009240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14009240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14009240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14009800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14012760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14012760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14012760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14012760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14013460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14014155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14014840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14015400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14016555000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14017240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14018920000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14019060000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14019340000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14020520000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14020660000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14020800000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14020940000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14021420000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14021580000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14021740000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14021900000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14024685000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14025040000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14025120000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14025440000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14026725000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14027980000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14028800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14029100000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14032980000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14033300000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14034660000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14034980000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14036640000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14036960000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14038845000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14039115000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14039620000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14039920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14040220000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14040520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14041485000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14041820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14042440000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14042740000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14044905000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14045240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14045860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14045940000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14046820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14047660000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14048520000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14048840000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14049160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14049700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14050480000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14050780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14052100000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14053260000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14053580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14054920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14055615000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14055940000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14056540000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14056840000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14057600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14061195000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14061580000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14062275000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14062660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14063265000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14063740000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14064720000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14064900000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14065220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14065780000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14066180000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14066720000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14066900000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14067220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14067760000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14068740000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14069060000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14069380000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14070075000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14070400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14071035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14071365000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14071700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14072235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14072420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14072740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14073280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14073797000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14073980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14074300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14074840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14075475000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14075660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14075980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14076520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14077035000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14077220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14077540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14078080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14078595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14078780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14079100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14079640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14080335000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14080520000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14080840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14081380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14082015000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14082345000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14082680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14083215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14083400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14083720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14084205000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14084400000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14084720000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14085280000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14086875000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14087060000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14087380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14087920000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14088705000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14088900000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14089220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14089780000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14093265000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14093445000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14093625000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14094135000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14094345000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14094525000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14095155000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14095335000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14095935000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14096475000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14096805000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14097495000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14097675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14098485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14101395000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14101605000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14101965000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14102325000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14111055000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14129980000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14130820000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14135160000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14135960000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14136660000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14137740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14139120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14139680000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14146800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14147560000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14148300000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14149455000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14152780000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14153760000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14154700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14155500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14156100000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14188935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14189340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14189775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14190180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14191605000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14192235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14192865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14193465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14194035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14195540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14195540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14195540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14195540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14196240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14197620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14197620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14197620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14197620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14198320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14201380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14201380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14201380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14201380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14202080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14202795000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14203480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14204040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14205195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14205880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14207775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14208180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14208615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14209020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14210445000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14211075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14211705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14212305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14212875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14214380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14214380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14214380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14214380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14215080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14216460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14216460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14216460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14216460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14217160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14220220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14220220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14220220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14220220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14220920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14221635000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14222320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14222880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14224035000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14224720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14226615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14227020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14227455000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14227860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14229285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14229915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14230545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14231145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14231715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14233220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14233220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14233220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14233220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14233920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14235300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14235300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14235300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14235300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14236000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14239060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14239060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14239060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14239060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14239760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14240475000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14241160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14241720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14242875000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14243560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14245240000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14245380000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14245660000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14246840000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14246980000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14247120000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14247260000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14247740000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14247900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14248060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14248220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14251005000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14251360000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14251440000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14251760000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14253045000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14254300000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14255120000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14255420000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14259540000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14259860000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14261220000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14261540000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14263200000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14263520000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14265435000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14265735000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14266180000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14266480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14266780000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14267080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14268075000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14268400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14269000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14269300000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14271525000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14271860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14272480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14272560000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14273440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14274280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14275140000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14275460000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14275780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14276320000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14277100000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14277400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14278720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14279980000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14280280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14281600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14282295000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14282620000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14283220000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14283520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14284280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14287905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14288300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14289045000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14289440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14290095000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14290580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14291580000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14291760000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14292080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14292640000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14293040000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14293720000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14293880000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14294200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14294740000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14295720000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14296040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14296360000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14297085000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14297420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14298075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14298405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14298740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14299275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14299460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14299780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14300320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14300867000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14301060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14301380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14301940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14302575000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14302760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14303080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14303620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14304135000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14304320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14304640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14305180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14305695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14305880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14306200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14306740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14307465000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14307660000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14307980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14308540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14309175000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14309505000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14309840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14310375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14310560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14310880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14311395000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14311580000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14311900000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14312440000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14314035000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14314220000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14314540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14315080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14315865000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14316060000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14316380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14316940000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14320455000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14320665000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14320875000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14321385000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14321625000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14321835000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14322465000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14322675000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14323305000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14323875000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14324235000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14324955000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14325165000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14326005000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14328945000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14329185000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14329575000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14329965000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14338725000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14357700000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14358540000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14363020000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14363820000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14364520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14365600000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14366960000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14367660000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14374880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14375740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14376580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14377605000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14381240000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14382120000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14383060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14383860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14384460000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14418285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14418800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14419275000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14419780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14421225000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14421885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14422515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14423205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14423895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14425560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14425560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14425560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14425560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14426260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14427720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14427720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14427720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14427720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14428420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14431480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14431480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14431480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14431480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14432180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14432895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14433580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14434140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14435295000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14435980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14437905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14438420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14438895000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14439400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14440845000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14441505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14442135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14442825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14443515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14445180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14445180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14445180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14445180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14445880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14447340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14447340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14447340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14447340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14448040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14451100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14451100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14451100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14451100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14451800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14452515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14453200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14453760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14454915000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14455600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14457525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14458040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14458515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14459020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14460465000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14461125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14461755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14462445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14463135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14464800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14464800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14464800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14464800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14465500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14466960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14466960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14466960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14466960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14467660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14470720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14470720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14470720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14470720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14471420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14472135000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14472820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14473380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14474535000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14475220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14476900000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14477040000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14477320000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14478500000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14478640000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14478780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14478920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14479400000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14479560000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14479720000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14479880000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14482815000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14483200000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14483280000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14483600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14484885000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14486140000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14486960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14487260000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14491800000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14492120000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14493780000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14494100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14495920000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14496220000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14498265000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14498595000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14499140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14499460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14499760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14500060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14501085000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14501420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14502040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14502340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14504625000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14504960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14505580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14505660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14506540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14507380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14508380000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14508700000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14509000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14509540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14510320000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14510620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14512040000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14513300000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14513620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14515040000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14515755000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14516080000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14516680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14516980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14517740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14521695000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14522080000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14522835000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14523220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14523885000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14524360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14525480000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14525660000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14525980000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14526520000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14526920000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14527600000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14527760000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14528080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14528620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14529740000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14530060000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14530360000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14531115000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14531440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14532075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14532405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14532740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14533275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14533460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14533780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14534320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14534897000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14535080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14535400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14535940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14536575000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14536760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14537080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14537620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14538135000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14538320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14538640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14539180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14539695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14539880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14540200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14540740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14541495000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14541680000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14542000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14542540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14543175000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14543505000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14543840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14544375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14544560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14544880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14545425000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14545620000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14545940000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14546500000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14548095000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14548280000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14548600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14549140000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14549925000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14550120000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14550440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14551000000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14554545000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14554785000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14555025000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14555595000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14555865000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14556105000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14556795000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14557035000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14557695000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14558295000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14558685000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14559435000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14559675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14560545000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14563515000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14563785000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14564205000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14564625000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14573415000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14592340000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14593320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14597940000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14598740000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14599440000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14600620000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14602080000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14602780000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14610140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14611000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14611840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14612895000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14616620000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14617500000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14618440000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14619240000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14619840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14653935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14654420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14654925000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14655400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14656875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14657565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14658225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14658885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14659575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14661240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14661240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14661240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14661240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14661940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14663400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14663400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14663400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14663400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14664100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14667160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14667160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14667160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14667160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14667860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14668575000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14669260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14669820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14670975000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14671660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14673615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14674100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14674605000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14675080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14676555000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14677245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14677905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14678565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14679255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14680920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14680920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14680920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14680920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14681620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14683080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14683080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14683080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14683080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14683780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14686840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14686840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14686840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14686840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14687540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14688255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14688940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14689500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14690655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14691340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14693295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14693780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14694285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14694760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14696235000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14696925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14697585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14698245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14698935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14700600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14700600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14700600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14700600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14701300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14702760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14702760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14702760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14702760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14703460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14706520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14706520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14706520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14706520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14707220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14707935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14708620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14709180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14710335000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14711020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14712700000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14712840000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14713120000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14714300000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14714440000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14714580000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14714720000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14715200000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14715360000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14715520000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14715680000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14718615000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14719000000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14719080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14719400000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14720685000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14721940000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14722760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14723060000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14727600000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14727920000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14729580000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14729900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14731720000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14732020000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14734095000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14734455000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14734940000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14735260000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14735560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14735860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14736915000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14737240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14737840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14738140000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14740485000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14740820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14741440000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14741520000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14742400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14743240000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14744240000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14744560000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14744860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14745400000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14746280000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14746600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14748020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14749280000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14749600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14751020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14751735000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14752060000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14752660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14752960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14753720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14757705000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14758100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14758905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14759300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14760015000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14760500000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14761640000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14761820000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14762140000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14762680000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14763080000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14763760000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14763920000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14764240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14764780000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14765900000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14766220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14766520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14767305000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14767640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14768295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14768625000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14768960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14769495000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14769680000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14770000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14770540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14771147000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14771340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14771660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14772220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14772855000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14773040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14773360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14773900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14774415000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14774600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14774920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14775460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14775975000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14776160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14776480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14777020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14777805000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14778000000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14778320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14778880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14779515000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14779845000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14780180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14780715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14780900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14781220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14781795000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14781980000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14782300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14782840000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14784435000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14784620000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14784940000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14785480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14786265000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14786460000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14786780000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14787340000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14790915000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14791185000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14791455000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14792025000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14792325000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14792595000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14793285000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14793555000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14794245000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14794875000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14795295000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14796075000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14796345000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14797245000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14800245000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14800545000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14800995000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14801445000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14810265000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14829340000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14830320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14835080000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14836020000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14836860000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14838040000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14839500000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14840200000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14847640000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14848480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14849320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14850405000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14854140000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14855020000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14855940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14856760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14857360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14859800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14860815000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14861140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14862200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14862915000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14863240000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14864460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14865975000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14866300000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14877560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14891775000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14892100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14892780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14893100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14893500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14894300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14894620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14894920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14895220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14895600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14896005000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14896080000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14897080000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14897380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14897760000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14899580000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14899900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14900200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14900500000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14900880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14901285000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14901360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14903960000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14906610000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14908460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14911110000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14912800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14913100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14913180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14913820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14914120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14914200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14914840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14915140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14915220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14915860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14916160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14916240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14917840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14918140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14918220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14918860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14919160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14919240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14919880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14920180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14920260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14920900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14921200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14921280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14922880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14923720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14924020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14924100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14924740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14925580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14925880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14925960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14926600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14927440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14927740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14927820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14928460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14929300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14929600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14929680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14931280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14932120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14932635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14932700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14933320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14934160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14934675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14934740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14935360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14936200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14936715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14936780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14937400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14938240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14938755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14938820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14939265000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14939595000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14939925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14940255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14940585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14940915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14941245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14943080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14944095000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14944420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14945480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14946195000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14946520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14947740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14949255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14949580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14960840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14975055000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14975380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14976060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14976380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14976780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14977580000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14977900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14978200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14978500000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14978880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14979285000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14979360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14980360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14980660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14981040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14982860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14983180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14983480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14983780000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14984160000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14984565000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14984640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14987240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14989890000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14991740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14994390000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14996080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14996380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14996460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14997100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14997400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14997480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14998120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14998420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14998500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14999140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14999440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 14999520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15001120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15001420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15001500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15002140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15002440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15002520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15003160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15003460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15003540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15004180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15004480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15004560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15006160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15007000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15007300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15007380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15008020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15008860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15009160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15009240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15009880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15010720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15011020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15011100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15011740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15012580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15012880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15012960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15014560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15015400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15015915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15015980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15016600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15017440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15017955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15018020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15018640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15019480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15019995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15020060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15020680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15021520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15022035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15022100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15022545000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15022875000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15023205000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15023535000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15023865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15024195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15024525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15026360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15027375000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15027700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15028760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15029475000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15029800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15031020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15032535000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15032860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15044120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15058335000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15058660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15059340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15059660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15060060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15060860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15061180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15061480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15061780000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15062160000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15062565000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15062640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15063640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15063940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15064320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15066140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15066460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15066760000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15067060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15067440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15067845000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15067920000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15070520000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15073170000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15075020000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15077670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15079360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15079660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15079740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15080380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15080680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15080760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15081400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15081700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15081780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15082420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15082720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15082800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15084400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15084700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15084780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15085420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15085720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15085800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15086440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15086740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15086820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15087460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15087760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15087840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15089440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15090280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15090580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15090660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15091300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15092140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15092440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15092520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15093160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15094000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15094300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15094380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15095020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15095860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15096160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15096240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15097840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15098680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15099195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15099260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15099880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15100720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15101235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15101300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15101920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15102760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15103275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15103340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15103960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15104800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15105315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15105380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15105825000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15106155000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15106485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15106815000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15107145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15107475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15107805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15109640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15110655000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15110980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15112040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15112755000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15113080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15114300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15115815000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15116140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15127400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15141615000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15141940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15142620000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15142940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15143340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15144140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15144460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15144760000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15145060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15145440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15145845000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15145920000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15146920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15147220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15147600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15149420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15149740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15150040000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15150340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15150720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15151125000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15151200000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15153800000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15156450000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15158300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15160950000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15162640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15162940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15163020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15163660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15163960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15164040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15164680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15164980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15165060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15165700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15166000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15166080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15167680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15167980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15168060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15168700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15169000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15169080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15169720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15170020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15170100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15170740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15171040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15171120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15172720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15173560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15173860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15173940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15174580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15175420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15175720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15175800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15176440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15177280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15177580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15177660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15178300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15179140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15179440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15179520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15181120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15181960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15182475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15182540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15183160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15184000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15184515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15184580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15185200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15186040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15186555000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15186620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15187240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15188080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15188595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15188660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15189105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15189435000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15189765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15190095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15190425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15190755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15191085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15193185000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15193815000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15194140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15194655000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15195255000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15195580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15196095000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15196695000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15197020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15197565000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15198195000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15198520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15199425000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15200055000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15200380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15201285000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15201915000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15202240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15203655000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15204255000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15204580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15205995000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15206595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15206920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15207765000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15208100000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15210105000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15210735000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15211060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15224000000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15234020000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15255400000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15258080000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15258795000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15270680000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15281300000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15282435000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15283425000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15283875000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15284235000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15284595000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15285375000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15286065000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15286755000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15288465000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15288825000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15289605000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15290295000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15291645000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15291825000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15292035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15292245000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15292425000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15292635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15292845000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15293025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15293205000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15293385000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15293595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15293805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15294015000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15294555000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15294880000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15299145000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15302565000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15304440000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15309740000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15312570000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15346905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15347300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15347715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15348260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15349605000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15350235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15350865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15351435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15352035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15353600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15353600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15353600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15353600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15354240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15355640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15355640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15355640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15355640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15356280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15359000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15359000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15359000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15359000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15359640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15360375000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15361000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15361640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15362835000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15363460000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15365565000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15366100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15366525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15367060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15368385000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15369015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15369645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15370215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15370815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15372380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15372380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15372380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15372380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15373020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15374420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15374420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15374420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15374420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15375060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15377780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15377780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15377780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15377780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15378420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15379155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15379780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15380420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15381615000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15382240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15384345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15384880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15385305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15385840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15387165000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15387795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15388425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15388995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15389595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15391160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15391160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15391160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15391160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15391800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15393200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15393200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15393200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15393200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15393840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15396560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15396560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15396560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15396560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15397200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15397935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15398560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15399200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15400395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15401020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15402940000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15403100000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15403380000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15404740000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15404900000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15405040000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15405180000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15405720000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15405900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15406060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15406220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15409275000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15409680000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15409760000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15410100000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15411495000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15412900000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15413800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15414120000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15418260000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15418600000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15420140000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15420480000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15422240000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15422580000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15424605000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15424875000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15425400000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15425740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15426060000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15426400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15427455000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15427800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15428460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15428800000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15430995000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15431340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15432000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15432080000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15433020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15433980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15434960000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15435300000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15435640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15436240000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15437040000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15437380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15438720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15439880000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15440220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15441560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15442275000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15442620000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15443280000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15443620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15444460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15448455000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15448860000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15449595000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15450000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15450645000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15451140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15452260000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15452420000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15452760000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15453360000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15453800000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15454420000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15454580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15454920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15455520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15456640000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15456960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15457300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15458055000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15458400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15459075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15459405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15459760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15460305000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15460500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15460840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15461440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15461987000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15462180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15462520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15463120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15463785000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15463980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15464320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15464920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15465465000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15465660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15466000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15466600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15467145000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15467340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15467680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15468280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15469035000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15469220000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15469560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15470160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15470835000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15471165000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15471520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15472065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15472260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15472600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15473115000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15473300000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15473640000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15474240000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15476025000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15476220000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15476560000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15477160000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15478065000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15478260000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15478600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15479200000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15482925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15483105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15483285000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15483795000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15484005000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15484185000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15484785000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15484965000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15485565000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15486135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15486435000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15487125000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15487305000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15488085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15492225000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15492435000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15492765000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15493095000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15500115000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15517820000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15518620000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15522900000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15523720000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15524360000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15525400000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15526800000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15527440000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15534140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15534980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15535820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15537015000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15539960000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15540880000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15541840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15542680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15543280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15577575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15578080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15578535000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15579040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15580395000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15581055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15581685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15582255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15582825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15584360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15584360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15584360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15584360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15585000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15586400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15586400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15586400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15586400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15587040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15589760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15589760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15589760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15589760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15590400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15591135000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15591760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15592400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15593595000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15594220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15596355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15596860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15597315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15597820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15599175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15599835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15600465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15601035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15601605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15603140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15603140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15603140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15603140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15603780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15605180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15605180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15605180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15605180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15605820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15608540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15608540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15608540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15608540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15609180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15609915000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15610540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15611180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15612375000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15613000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15615135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15615640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15616095000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15616600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15617955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15618615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15619245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15619815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15620385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15622560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15623960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15623960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15623960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15623960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15624600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15627320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15627320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15627320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15627320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15627960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15628695000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15629320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15629960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15631155000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15631780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15633700000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15633860000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15634140000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15635500000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15635660000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15635800000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15635940000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15636480000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15636660000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15636820000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15636980000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15640035000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15640440000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15640520000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15640860000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15642255000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15643660000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15644560000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15644880000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15649020000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15649360000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15650900000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15651240000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15653000000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15653340000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15655395000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15655695000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15656160000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15656500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15656820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15657160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15658245000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15658600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15659260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15659580000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15661845000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15662200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15662860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15662940000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15663880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15664800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15665780000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15666120000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15666460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15667060000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15667860000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15668200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15669540000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15670700000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15671040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15672380000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15673095000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15673440000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15674100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15674440000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15675280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15679305000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15679720000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15680505000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15680920000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15681615000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15682120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15683240000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15683420000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15683760000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15684360000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15684800000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15685420000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15685580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15685920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15686520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15687640000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15687960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15688300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15689085000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15689440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15690105000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15690435000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15690780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15691335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15691520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15691860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15692460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15693047000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15693240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15693580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15694180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15694845000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15695040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15695380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15695980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15696525000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15696720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15697060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15697660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15698205000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15698400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15698740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15699340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15700125000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15700320000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15700660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15701260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15701925000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15702255000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15702600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15703155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15703340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15703680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15704235000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15704420000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15704760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15705360000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15707145000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15707340000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15707680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15708280000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15709185000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15709380000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15709720000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15710320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15714075000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15714285000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15714495000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15715035000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15715275000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15715485000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15716115000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15716325000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15716955000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15717555000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15717885000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15718605000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15718815000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15719625000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15723795000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15724035000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15724395000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15724755000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15731805000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15749480000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15750440000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15754720000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15755540000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15756340000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15757380000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15758780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15759420000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15766260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15767120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15767960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15769065000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15772260000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15773060000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15774000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15774840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15775440000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15809745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15810240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15810705000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15811200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15812595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15813285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15813915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15814605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15815295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15816920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15816920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15816920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15816920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15817560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15818960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15818960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15818960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15818960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15819600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15822320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15822320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15822320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15822320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15823120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15823875000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15824500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15825140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15826335000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15826960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15829125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15829600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15830085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15830560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15831945000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15832635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15833265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15833955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15834675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15836300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15836300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15836300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15836300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15836940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15838340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15838340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15838340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15838340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15838980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15841700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15841700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15841700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15841700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15842500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15843255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15843880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15844520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15845715000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15846340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15848505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15848980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15849465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15849940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15851325000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15852015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15852645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15853335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15854055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15855680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15855680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15855680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15855680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15856320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15857720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15857720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15857720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15857720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15858360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15861080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15861080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15861080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15861080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15861880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15862635000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15863260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15863900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15865095000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15865720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15867640000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15867800000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15868080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15869440000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15869600000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15869740000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15869880000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15870420000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15870600000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15870760000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15870920000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15873975000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15874380000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15874460000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15874800000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15876195000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15877600000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15878500000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15878820000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15883080000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15883420000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15884960000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15885300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15887060000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15887400000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15889485000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15889815000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15890380000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15890700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15891040000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15891360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15892485000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15892840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15893500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15893820000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15896145000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15896500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15897160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15897240000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15898180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15899100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15900080000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15900420000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15900760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15901360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15902160000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15902500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15903840000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15905120000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15905460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15906800000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15907515000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15907860000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15908520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15908860000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15909700000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15913755000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15914160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15914955000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15915360000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15916065000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15916560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15917680000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15917840000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15918180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15918780000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15919220000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15919840000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15920000000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15920340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15920940000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15922060000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15922380000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15922720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15923535000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15923880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15924555000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15924885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15925240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15925785000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15925980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15926320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15926920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15927527000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15927720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15928060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15928660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15929325000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15929520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15929860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15930460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15931005000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15931200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15931540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15932140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15932685000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15932880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15933220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15933820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15934635000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15934820000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15935160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15935760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15936435000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15936765000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15937120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15937665000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15937860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15938200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15938775000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15938960000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15939300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15939900000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15941685000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15941880000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15942220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15942820000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15943725000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15943920000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15944260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15944860000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15948825000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15949065000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15949305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15949875000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15950145000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15950385000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15951045000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15951285000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15951945000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15952575000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15952935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15953685000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15953925000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15954765000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15958965000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15959235000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15959625000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15960015000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15967095000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15986660000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15987620000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15992200000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15993020000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15993820000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15994860000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15996260000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 15996900000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16003740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16004600000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16005440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16006575000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16009880000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16010800000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16011760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16012600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16013200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16047795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16048400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16048905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16049520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16050945000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16051665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16052295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16052985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16053705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16055420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16055420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16055420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16055420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16056220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16057620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16057620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16057620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16057620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16058420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16061240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16061240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16061240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16061240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16062040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16062795000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16063420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16064060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16065255000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16065880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16068075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16068680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16069185000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16069800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16071225000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16071945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16072575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16073265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16073985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16075700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16075700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16075700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16075700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16076500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16078700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16081520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16081520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16081520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16081520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16082320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16083075000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16083700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16084340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16085535000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16086160000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16088355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16088960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16089465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16090080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16091505000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16092225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16092855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16093545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16094265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16095980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16095980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16095980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16095980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16096780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16098180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16098180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16098180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16098180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16098980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16101800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16101800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16101800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16101800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16102600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16103355000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16103980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16104620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16105815000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16106440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16108360000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16108520000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16108800000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16110160000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16110320000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16110460000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16110600000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16111140000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16111320000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16111480000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16111640000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16114695000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16115100000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16115180000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16115520000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16116915000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16118320000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16119220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16119540000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16123800000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16124140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16125680000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16126020000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16127780000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16128120000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16130235000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16130595000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16131100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16131420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16131760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16132080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16133235000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16133580000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16134240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16134580000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16136955000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16137300000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16137960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16138040000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16138980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16139940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16140920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16141260000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16141600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16142200000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16143000000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16143340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16144680000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16145960000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16146300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16147760000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16148475000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16148820000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16149480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16149820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16150660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16154745000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16155160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16156005000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16156420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16157175000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16157680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16158800000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16158980000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16159320000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16159920000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16160360000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16161140000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16161320000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16161660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16162260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16163540000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16163880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16164220000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16165065000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16165420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16166085000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16166415000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16166760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16167315000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16167500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16167840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16168440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16169087000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16169280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16169620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16170220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16170885000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16171080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16171420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16172020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16172565000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16172760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16173100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16173700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16174245000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16174440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16174780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16175380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16176225000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16176420000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16176760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16177360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16178025000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16178355000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16178700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16179255000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16179440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16179780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16180395000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16180580000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16180920000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16181520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16183305000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16183500000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16183840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16184440000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16185345000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16185540000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16185880000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16186480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16190475000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16190745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16191015000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16191615000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16191915000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16192185000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16192875000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16193145000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16193835000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16194495000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16194885000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16195665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16195935000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16196805000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16201035000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16201335000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16201755000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16202175000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16209285000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16228820000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16229780000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16234360000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16235180000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16235980000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16237020000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16238540000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16239340000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16246400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16247360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16248320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16249485000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16252800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16253720000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16254660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16255500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16256100000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16258880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16260045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16260400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16261640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16262565000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16262920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16264360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16266105000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16266460000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16279700000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16296195000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16296540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16297340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16297680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16298100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16299000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16299340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16299660000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16300000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16300400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16300875000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16300940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16302120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16302460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16302860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16304960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16305300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16305640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16305960000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16306380000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16306845000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16306920000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16309980000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16312800000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16315020000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16317840000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16319760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16320100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16320180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16320900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16321240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16321320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16322040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16322380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16322460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16323180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16323520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16323600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16325400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16325740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16325820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16326540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16326880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16326960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16327680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16328020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16328100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16328820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16329160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16329240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16331040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16331980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16332300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16332380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16333080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16334020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16334340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16334420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16335120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16336060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16336380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16336460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16337160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16338100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16338420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16338500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16340280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16341220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16341795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16341860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16342560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16343500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16344075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16344140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16344840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16345780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16346355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16346420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16347120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16348060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16348635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16348700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16349145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16349475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16349805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16350135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16350465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16350795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16351125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16353240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16354395000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16354740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16355980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16356885000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16357240000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16358680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16360425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16360780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16374020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16390515000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16390860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16391660000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16392000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16392420000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16393320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16393660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16393980000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16394320000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16394720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16395195000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16395260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16396440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16396780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16397180000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16399280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16399620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16399960000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16400280000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16400700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16401165000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16401240000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16404300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16407120000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16409340000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16412160000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16414080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16414420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16414500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16415220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16415560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16415640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16416360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16416700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16416780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16417500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16417840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16417920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16419720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16420060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16420140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16420860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16421200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16421280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16422000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16422340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16422420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16423140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16423480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16423560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16425360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16426300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16426620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16426700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16427400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16428340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16428660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16428740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16429440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16430380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16430700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16430780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16431480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16432420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16432740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16432820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16434600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16435540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16436115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16436180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16436880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16437820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16438395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16438460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16439160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16440100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16440675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16440740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16441440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16442380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16442955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16443020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16443465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16443795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16444125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16444455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16444785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16445115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16445445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16447560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16448715000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16449060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16450300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16451205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16451560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16453000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16454745000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16455100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16468340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16484835000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16485180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16485980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16486320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16486740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16487640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16487980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16488300000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16488640000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16489040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16489515000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16489580000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16490760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16491100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16491500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16493600000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16493940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16494280000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16494600000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16495020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16495485000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16495560000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16498620000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16501440000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16503660000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16506480000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16508400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16508740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16508820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16509540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16509880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16509960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16510680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16511020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16511100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16511820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16512160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16512240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16514040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16514380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16514460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16515180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16515520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16515600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16516320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16516660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16516740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16517460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16517800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16517880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16519680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16520620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16520940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16521020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16521720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16522660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16522980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16523060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16523760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16524700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16525020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16525100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16525800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16526740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16527060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16527140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16528920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16529860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16530435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16530500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16531200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16532140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16532715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16532780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16533480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16534420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16534995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16535060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16535760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16536700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16537275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16537340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16537785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16538115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16538445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16538775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16539105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16539435000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16539765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16541880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16543035000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16543380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16544620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16545525000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16545880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16547320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16549065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16549420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16562660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16579155000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16579500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16580300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16580640000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16581060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16581960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16582300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16582620000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16582960000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16583360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16583835000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16583900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16585080000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16585420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16585820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16587920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16588260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16588600000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16588920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16589340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16589805000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16589880000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16592940000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16595760000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16597980000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16600800000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16602720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16603060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16603140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16603860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16604200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16604280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16605000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16605340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16605420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16606140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16606480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16606560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16608360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16608700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16608780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16609500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16609840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16609920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16610640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16610980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16611060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16611780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16612120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16612200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16614000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16614940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16615260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16615340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16616040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16616980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16617300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16617380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16618080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16619020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16619340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16619420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16620120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16621060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16621380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16621460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16623240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16624180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16624755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16624820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16625520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16626460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16627035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16627100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16627800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16628740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16629315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16629380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16630080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16631020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16631595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16631660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16632105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16632435000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16632765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16633095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16633425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16633755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16634085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16636455000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16637115000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16637460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16638045000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16638735000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16639080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16639665000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16640355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16640700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16641405000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16642095000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16642440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16643535000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16644195000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16644540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16645635000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16646295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16646640000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16648335000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16648995000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16649340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16651035000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16651695000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16652040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16653075000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16653420000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16655685000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16656375000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16656720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16671860000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16683760000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16709140000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16712160000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16712925000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16726880000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16739380000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16740645000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16741785000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16742220000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16742535000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16742865000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16743675000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16744395000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16745115000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16746980000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16747305000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16748115000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16748835000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16750335000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16750515000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16750725000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16750935000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16751115000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16751325000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16751535000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16751715000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16751895000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16752075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16752285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16752495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16752705000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16753305000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16753660000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16758285000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16761705000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16763740000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16769060000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16772010000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16807665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16808160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16808565000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16809060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16810335000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16810965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16811535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16812195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16812735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16814220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16814220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16814220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16814220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16814940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16816260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16816260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16816260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16816260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16816980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16819280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16819280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16819280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16819280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16820000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16820775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16821480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16822200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16823415000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16824120000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16826205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16826700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16827105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16827600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16828875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16829505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16830075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16830735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16831275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16832760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16832760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16832760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16832760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16833480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16834800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16834800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16834800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16834800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16835520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16837820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16837820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16837820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16837820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16838540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16839315000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16840020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16840740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16841955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16842660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16844745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16845240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16845645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16846140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16847415000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16848045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16848615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16849275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16849815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16851300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16851300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16851300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16851300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16852020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16853340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16853340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16853340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16853340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16854060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16856360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16856360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16856360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16856360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16857080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16857855000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16858560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16859280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16860495000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16861200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16863180000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16863360000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16863640000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16865160000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16865340000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16865480000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16865620000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16866220000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16866420000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16866580000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16866740000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16869975000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16870400000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16870480000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16870820000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16872285000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16873760000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16874720000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16875060000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16879340000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16879700000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16881420000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16881780000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16883580000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16883940000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16886085000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16886355000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16886840000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16887200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16887560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16887920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16889055000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16889420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16890140000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16890500000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16892685000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16893060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16893780000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16893860000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16894860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16895840000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16896920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16897280000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16897640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16898280000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16899060000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16899420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16900660000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16901880000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16902240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16903480000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16904235000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16904600000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16905320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16905680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16906580000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16910805000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16911240000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16911975000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16912400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16913085000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16913600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16914840000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16915020000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16915380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16916000000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16916460000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16917160000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16917320000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16917680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16918320000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16919520000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16919880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16920240000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16921005000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16921380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16922055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16922385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16922760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16923315000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16923500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16923860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16924500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16925057000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16925240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16925600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16926240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16926915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16927100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16927460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16928100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16928655000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16928840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16929200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16929840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16930395000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16930580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16930940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16931580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16932345000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16932540000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16932900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16933520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16934205000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16934535000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16934900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16935465000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16935660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16936020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16936545000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16936740000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16937100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16937720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16939545000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16939740000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16940100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16940720000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16941585000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16941780000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16942140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16942760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16946625000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16946805000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16946985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16947525000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16947735000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16947915000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16948515000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16948695000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16949295000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16949895000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16950165000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16950885000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16951065000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16951845000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16957215000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16957425000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16957725000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16958025000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16963335000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16980060000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16980960000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16985160000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16986000000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16986720000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16987640000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16988980000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16989700000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16995740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16996560000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16997360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 16998645000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17001280000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17002200000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17003160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17004000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17004600000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17040195000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17040660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17041095000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17041560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17042865000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17043555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17044245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17044935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17045625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17047200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17047200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17047200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17047200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17047920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17049240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17049240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17049240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17049240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17049960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17052400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17052400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17052400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17052400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17053120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17053875000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17054580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17055300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17056515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17057220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17059335000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17059800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17060235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17060700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17062005000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17062695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17063385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17064075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17064765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17066340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17066340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17066340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17066340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17067060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17068380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17068380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17068380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17068380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17069100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17071540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17071540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17071540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17071540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17072260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17073015000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17073720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17074440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17075655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17076360000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17078475000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17078940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17079375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17079840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17081145000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17081835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17082525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17083215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17083905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17085480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17085480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17085480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17085480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17086200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17087520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17087520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17087520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17087520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17088240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17090680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17090680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17090680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17090680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17091400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17092155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17092860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17093580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17094795000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17095500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17097480000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17097660000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17097940000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17099460000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17099640000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17099780000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17099920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17100520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17100720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17100880000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17101040000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17104275000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17104700000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17104780000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17105120000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17106585000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17108060000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17109020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17109360000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17113780000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17114120000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17115840000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17116200000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17118000000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17118360000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17120535000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17120835000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17121440000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17121800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17122160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17122520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17123685000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17124060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17124780000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17125140000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17127345000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17127720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17128440000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17128520000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17129520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17130500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17131580000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17131940000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17132300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17132940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17133720000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17134080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17135320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17136540000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17136900000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17138140000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17138895000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17139260000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17139980000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17140340000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17141240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17145495000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17145920000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17146725000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17147160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17147835000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17148360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17149560000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17149740000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17150100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17150720000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17151180000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17151880000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17152040000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17152400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17153040000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17154240000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17154600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17154960000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17155755000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17156120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17156805000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17157135000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17157500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17158065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17158260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17158620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17159240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17159837000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17160020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17160380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17161020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17161695000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17161880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17162240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17162880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17163435000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17163620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17163980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17164620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17165175000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17165360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17165720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17166360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17167155000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17167340000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17167700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17168340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17169015000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17169345000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17169720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17170275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17170460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17170820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17171385000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17171580000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17171940000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17172560000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17174385000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17174580000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17174940000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17175560000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17176425000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17176620000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17176980000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17177600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17181495000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17181705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17181915000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17182485000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17182725000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17182935000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17183565000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17183775000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17184405000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17185065000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17185365000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17186115000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17186325000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17187135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17192535000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17192775000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17193105000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17193435000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17198775000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17217580000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17218480000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17222820000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17223660000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17224380000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17225300000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17226640000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17227360000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17233840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17234800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17235760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17236965000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17239740000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17240520000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17241480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17242320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17242920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17278545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17279160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17279625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17280240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17281575000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17282265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17282955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17283645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17284335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17286020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17286020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17286020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17286020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17286740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17288220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17288220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17288220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17288220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17288940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17291380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17291380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17291380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17291380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17292100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17292855000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17293560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17294280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17295495000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17296200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17298345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17298960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17299425000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17300040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17301375000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17302065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17302755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17303445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17304135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17305820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17305820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17305820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17305820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17306540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17308020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17308020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17308020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17308020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17308740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17311180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17311180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17311180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17311180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17311900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17312655000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17313360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17314080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17315295000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17316000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17318145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17318760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17319225000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17319840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17321175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17321865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17322555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17323245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17323935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17325620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17325620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17325620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17325620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17326340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17327820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17327820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17327820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17327820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17328540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17330980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17330980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17330980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17330980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17331700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17332455000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17333160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17333880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17335095000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17335800000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17337780000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17337960000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17338240000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17339760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17339940000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17340080000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17340220000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17340820000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17341020000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17341180000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17341340000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17344575000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17345000000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17345080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17345420000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17346885000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17348360000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17349320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17349660000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17354080000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17354420000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17356140000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17356500000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17358300000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17358660000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17360865000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17361195000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17361740000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17362100000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17362460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17362820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17364015000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17364380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17365100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17365460000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17367765000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17368140000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17368860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17368940000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17369940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17370920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17372000000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17372360000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17372720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17373360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17374140000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17374500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17375880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17377100000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17377460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17378860000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17379615000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17379980000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17380700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17381060000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17381960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17386245000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17386680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17387475000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17387900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17388645000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17389160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17390400000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17390580000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17390940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17391560000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17392020000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17392720000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17392880000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17393240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17393880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17395080000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17395440000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17395800000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17396625000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17397000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17397675000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17398005000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17398380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17398935000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17399120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17399480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17400120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17400737000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17400920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17401280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17401920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17402595000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17402780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17403140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17403780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17404335000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17404520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17404880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17405520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17406075000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17406260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17406620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17407260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17408085000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17408280000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17408640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17409260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17409945000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17410275000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17410640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17411205000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17411400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17411760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17412345000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17412540000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17412900000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17413520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17415345000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17415540000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17415900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17416520000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17417385000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17417580000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17417940000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17418560000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17422485000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17422725000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17422965000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17423565000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17423835000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17424075000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17424735000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17424975000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17425635000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17426295000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17426625000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17427405000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17427645000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17428485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17433915000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17434185000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17434545000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17434905000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17440275000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17459080000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17460160000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17464680000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17465520000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17466240000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17467300000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17468780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17469500000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17476000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17476960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17477920000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17479155000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17482060000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17482980000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17483940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17484780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17485380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17521275000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17521860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17522355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17522940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17524305000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17525055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17525745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17526435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17527125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17528780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17528780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17528780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17528780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17529500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17530980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17530980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17530980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17530980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17531700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17534140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17534140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17534140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17534140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17534860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17535615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17536320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17537040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17538255000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17538960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17541135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17541720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17542215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17542800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17544165000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17544915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17545605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17546295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17546985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17548640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17548640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17548640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17548640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17549360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17550840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17550840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17550840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17550840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17551560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17554000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17554000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17554000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17554000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17554720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17555475000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17556180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17556900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17558115000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17558820000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17560995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17561580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17562075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17562660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17564025000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17564775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17565465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17566155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17566845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17568500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17568500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17568500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17568500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17569220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17570700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17570700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17570700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17570700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17571420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17573860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17573860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17573860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17573860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17574580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17575335000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17576040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17576760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17577975000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17578680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17580660000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17580840000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17581120000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17582640000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17582820000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17582960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17583100000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17583700000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17583900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17584060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17584220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17587455000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17587880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17587960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17588300000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17589765000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17591240000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17592200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17592540000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17597100000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17597460000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17599180000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17599520000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17601340000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17601680000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17603955000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17604315000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17604980000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17605340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17605700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17606060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17607285000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17607660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17608380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17608740000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17611065000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17611440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17612160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17612240000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17613240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17614220000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17615300000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17615660000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17616020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17616660000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17617580000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17617940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17619340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17620560000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17620920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17622300000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17623035000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17623400000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17624120000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17624480000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17625380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17629695000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17630120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17630985000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17631420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17632155000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17632680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17633880000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17634060000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17634420000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17635040000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17635500000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17636200000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17636360000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17636720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17637360000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17638560000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17638920000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17639280000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17640135000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17640500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17641185000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17641515000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17641880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17642445000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17642640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17643000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17643620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17644277000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17644460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17644820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17645460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17646135000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17646320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17646680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17647320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17647875000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17648060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17648420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17649060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17649615000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17649800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17650160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17650800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17651655000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17651840000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17652200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17652840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17653515000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17653845000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17654220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17654775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17654960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17655320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17655945000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17656140000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17656500000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17657120000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17658945000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17659140000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17659500000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17660120000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17660985000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17661180000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17661540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17662160000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17666115000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17666385000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17666655000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17667285000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17667585000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17667855000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17668545000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17668815000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17669505000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17670225000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17670585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17671395000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17671665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17672535000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17677995000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17678295000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17678685000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17679075000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17684475000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17703400000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17704480000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17709000000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17709840000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17710560000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17711620000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17713100000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17713820000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17720320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17721280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17722240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17723505000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17726420000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17727340000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17728320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17729160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17729760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17732600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17733435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17733800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17734940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17735595000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17735960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17737200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17738355000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17738720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17746460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17757555000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17757920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17758700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17759060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17759500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17760360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17760720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17761080000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17761440000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17761880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17762355000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17762420000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17763360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17763720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17764160000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17765640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17766000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17766360000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17766720000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17767160000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17767635000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17767700000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17770500000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17773140000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17775080000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17777730000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17779640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17780000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17780080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17780720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17781080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17781160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17781800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17782160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17782240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17782880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17783240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17783320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17785100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17785460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17785540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17786180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17786540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17786620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17787260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17787620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17787700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17788340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17788700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17788780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17790560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17791560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17791920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17792000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17792660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17793660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17794020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17794100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17794760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17795760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17796120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17796200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17796860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17797860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17798220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17798300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17800100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17801100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17801715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17801780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17802440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17803440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17804055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17804120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17804780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17805780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17806395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17806460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17807120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17808120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17808735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17808800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17809245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17809575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17809905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17810235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17810565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17810895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17811225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17813300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17814135000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17814500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17815640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17816295000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17816660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17817900000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17819055000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17819420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17827160000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17838255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17838620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17839400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17839760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17840200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17841060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17841420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17841780000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17842140000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17842580000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17843055000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17843120000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17844060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17844420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17844860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17846340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17846700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17847060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17847420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17847860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17848335000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17848400000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17851200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17853840000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17855780000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17858430000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17860340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17860700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17860780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17861420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17861780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17861860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17862500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17862860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17862940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17863580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17863940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17864020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17865800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17866160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17866240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17866880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17867240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17867320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17867960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17868320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17868400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17869040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17869400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17869480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17871260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17872260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17872620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17872700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17873360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17874360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17874720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17874800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17875460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17876460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17876820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17876900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17877560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17878560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17878920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17879000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17880800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17881800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17882415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17882480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17883140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17884140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17884755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17884820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17885480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17886480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17887095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17887160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17887820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17888820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17889435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17889500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17889945000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17890275000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17890605000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17890935000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17891265000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17891595000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17891925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17894000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17894835000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17895200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17896340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17896995000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17897360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17898600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17899755000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17900120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17907860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17918955000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17919320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17920100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17920460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17920900000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17921760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17922120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17922480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17922840000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17923280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17923755000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17923820000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17924760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17925120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17925560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17927040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17927400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17927760000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17928120000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17928560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17929035000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17929100000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17931900000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17934540000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17936480000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17939130000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17941040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17941400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17941480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17942120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17942480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17942560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17943200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17943560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17943640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17944280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17944640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17944720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17946500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17946860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17946940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17947580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17947940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17948020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17948660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17949020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17949100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17949740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17950100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17950180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17951960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17952960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17953320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17953400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17954060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17955060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17955420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17955500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17956160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17957160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17957520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17957600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17958260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17959260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17959620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17959700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17961500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17962500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17963115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17963180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17963840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17964840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17965455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17965520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17966180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17967180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17967795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17967860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17968520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17969520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17970135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17970200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17970645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17970975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17971305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17971635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17971965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17972295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17972625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17974700000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17975535000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17975900000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17977040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17977695000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17978060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17979300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17980455000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17980820000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17988560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 17999655000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18000020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18000800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18001160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18001600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18002460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18002820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18003180000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18003540000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18003980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18004455000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18004520000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18005460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18005820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18006260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18007740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18008100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18008460000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18008820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18009260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18009735000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18009800000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18012600000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18015240000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18017180000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18019830000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18021740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18022100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18022180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18022820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18023180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18023260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18023900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18024260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18024340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18024980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18025340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18025420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18027200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18027560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18027640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18028280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18028640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18028720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18029360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18029720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18029800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18030440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18030800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18030880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18032660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18033660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18034020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18034100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18034760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18035760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18036120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18036200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18036860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18037860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18038220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18038300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18038960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18039960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18040320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18040400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18042200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18043200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18043815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18043880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18044540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18045540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18046155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18046220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18046880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18047880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18048495000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18048560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18049220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18050220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18050835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18050900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18051345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18051675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18052005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18052335000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18052665000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18052995000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18053325000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18055665000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18056385000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18056760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18057285000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18058005000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18058380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18058905000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18059625000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18060000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18060585000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18061305000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18061680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18062475000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18063165000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18063540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18064335000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18065025000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18065400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18066525000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18067245000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18067620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18068745000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18069465000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18069840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18070575000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18070940000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18073185000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18073905000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18074280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18083780000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18090380000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18104440000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18107360000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18108075000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18116480000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18123440000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18124395000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18125205000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18125595000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18125895000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18126195000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18126915000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18127545000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18128175000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18130005000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18130305000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18131025000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18131655000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18133155000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18133335000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18133545000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18133755000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18133935000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18134145000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18134355000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18134535000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18134715000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18134895000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18135105000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18135315000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18135525000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18136155000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18136520000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18141195000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18144375000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18145960000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18151280000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18154110000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18190845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18191440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18191865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18192440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18193665000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18194325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18194955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18195555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18196185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18197760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18197760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18197760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18197760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18198360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18199720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18199720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18199720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18199720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18200320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18202300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18202300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18202300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18202300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18203100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18203895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18204680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18205480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18206775000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18207560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18209865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18210460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18210885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18211460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18212685000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18213345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18213975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18214575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18215205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18216780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18216780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18216780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18216780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18217380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18218740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18218740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18218740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18218740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18219340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18221320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18221320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18221320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18221320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18222120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18222915000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18223700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18224500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18225795000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18226580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18228885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18229480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18229905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18230480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18231705000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18232365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18232995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18233595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18234225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18235800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18235800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18235800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18235800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18236400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18237760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18237760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18237760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18237760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18238360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18240340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18240340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18240340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18240340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18241140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18241935000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18242720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18243520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18244815000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18245600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18247840000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18248040000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18248320000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18249980000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18250180000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18250320000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18250460000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18251120000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18251340000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18251500000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18251660000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18255165000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18255580000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18255660000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18256040000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18257625000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18259120000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18260120000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18260480000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18264880000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18265240000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18266720000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18267100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18269080000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18269440000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18271785000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18272055000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18272640000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18273020000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18273400000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18273760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18274965000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18275360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18276100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18276460000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18278655000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18279040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18279760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18279840000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18280900000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18281920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18282880000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18283240000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18283600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18284260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18284980000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18285340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18286580000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18287660000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18288040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18289280000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18290055000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18290440000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18291160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18291520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18292460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18296835000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18297280000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18298035000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18298480000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18299145000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18299680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18300820000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18300980000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18301360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18302020000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18302480000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18303060000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18303240000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18303620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18304300000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18305440000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18305800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18306160000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18306975000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18307360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18308055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18308385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18308780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18309375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18309560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18309940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18310600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18311177000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18311360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18311740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18312400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18313095000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18313280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18313660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18314320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18314895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18315080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18315460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18316120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18316695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18316880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18317260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18317920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18318735000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18318920000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18319300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18319960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18320655000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18320985000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18321380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18321975000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18322160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18322540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18323085000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18323280000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18323660000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18324340000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18326295000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18326480000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18326860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18327520000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18328425000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18328620000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18329000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18329680000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18333885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18334065000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18334245000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18334815000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18335025000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18335205000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18335805000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18335985000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18336585000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18337245000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18337485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18338205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18338385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18339135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18345735000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18345945000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18346215000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18346485000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18350085000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18367020000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18368020000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18372180000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18372900000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18373500000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18374380000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18375720000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18376320000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18381960000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18382860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18383760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18385095000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18387320000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18388200000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18389200000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18390060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18390660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18428175000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18428740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18429195000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18429740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18430995000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18431685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18432315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18432945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18433545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18435100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18435100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18435100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18435100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18435900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18437260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18437260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18437260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18437260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18438060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18440060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18440060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18440060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18440060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18440860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18441615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18442400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18443200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18444495000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18445280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18447615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18448180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18448635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18449180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18450435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18451125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18451755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18452385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18452985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18454540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18454540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18454540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18454540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18455340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18456700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18456700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18456700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18456700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18457500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18459500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18459500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18459500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18459500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18460300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18461055000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18461840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18462640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18463935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18464720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18467055000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18467620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18468075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18468620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18469875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18470565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18471195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18471825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18472425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18473980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18473980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18473980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18473980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18474780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18476140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18476140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18476140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18476140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18476940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18478940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18478940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18478940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18478940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18479740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18480495000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18481280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18482080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18483375000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18484160000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18486400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18486600000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18486880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18488540000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18488740000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18488880000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18489020000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18489680000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18489900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18490060000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18490220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18493725000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18494140000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18494220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18494600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18496185000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18497680000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18498680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18499040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18503660000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18504040000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18505940000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18506320000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18508300000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18508660000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18511035000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18511335000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18511860000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18512240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18512620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18512980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18514215000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18514600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18515320000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18515680000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18517935000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18518320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18519040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18519120000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18520180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18521200000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18522360000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18522740000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18523120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18523780000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18524500000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18524860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18526100000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18527340000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18527720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18528980000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18529755000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18530140000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18530860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18531220000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18532160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18536805000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18537260000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18538065000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18538520000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18539235000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18539780000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18541140000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18541320000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18541700000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18542380000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18542840000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18543620000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18543800000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18544180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18544840000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18546180000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18546560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18546940000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18547785000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18548180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18548895000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18549225000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18549620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18550215000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18550400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18550780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18551440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18552047000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18552240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18552620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18553300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18553995000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18554180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18554560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18555220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18555795000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18555980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18556360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18557020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18557595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18557780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18558160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18558820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18559665000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18559860000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18560240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18560920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18561615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18561945000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18562340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18562935000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18563120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18563500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18564075000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18564260000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18564640000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18565300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18567255000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18567440000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18567820000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18568480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18569385000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18569580000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18569960000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18570640000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18574875000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18575085000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18575295000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18575865000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18576105000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18576315000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18576915000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18577125000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18577755000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18578445000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18578715000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18579465000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18579675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18580455000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18587085000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18587325000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18587625000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18587925000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18591555000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18608500000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18609500000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18613660000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18614380000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18615180000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18616060000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18617400000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18618200000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18624140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18625040000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18625940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18627255000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18629640000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18630520000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18631500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18632380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18632980000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18670485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18671020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18671505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18672020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18673305000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18674025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18674655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18675255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18675885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18677400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18677400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18677400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18677400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18678200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18679560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18679560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18679560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18679560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18680360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18682520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18682520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18682520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18682520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18683320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18684075000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18684860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18685660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18686955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18687740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18690105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18690640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18691125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18691640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18692925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18693645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18694275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18694875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18695505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18697020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18697020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18697020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18697020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18697820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18699180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18699180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18699180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18699180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18699980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18702140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18702140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18702140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18702140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18702940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18703695000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18704480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18705280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18706575000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18707360000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18709725000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18710260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18710745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18711260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18712545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18713265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18713895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18714495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18715125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18716640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18716640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18716640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18716640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18717440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18718800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18718800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18718800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18718800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18719600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18721760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18721760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18721760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18721760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18722560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18723315000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18724100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18724900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18726195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18726980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18729220000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18729420000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18729700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18731360000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18731560000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18731700000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18731840000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18732500000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18732720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18732880000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18733040000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18736545000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18736960000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18737040000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18737420000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18739005000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18740500000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18741500000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18741860000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18746480000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18746860000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18748760000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18749140000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18751120000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18751480000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18753885000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18754215000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18754880000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18755260000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18755620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18755980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18757245000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18757640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18758380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18758740000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18761055000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18761440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18762160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18762240000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18763300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18764320000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18765480000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18765860000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18766240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18766900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18767780000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18768160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18769400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18770640000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18771020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18772280000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18773055000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18773440000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18774160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18774520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18775460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18780135000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18780580000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18781395000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18781840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18782565000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18783100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18784440000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18784620000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18785000000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18785680000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18786140000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18786920000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18787100000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18787480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18788140000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18789480000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18789860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18790240000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18791115000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18791500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18792195000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18792525000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18792920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18793515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18793700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18794080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18794740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18795377000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18795560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18795940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18796600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18797295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18797480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18797860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18798520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18799095000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18799280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18799660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18800320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18800895000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18801080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18801460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18802120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18802995000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18803180000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18803560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18804220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18804915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18805245000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18805640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18806235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18806420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18806800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18807405000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18807600000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18807980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18808660000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18810615000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18810800000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18811180000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18811840000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18812745000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18812940000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18813320000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18814000000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18818265000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18818505000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18818745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18819375000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18819645000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18819885000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18820545000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18820785000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18821445000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18822165000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18822465000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18823245000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18823485000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18824295000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18830955000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18831225000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18831555000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18831885000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18835545000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18852500000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18853500000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18857800000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18858660000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18859460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18860340000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18861700000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18862500000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18868440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18869340000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18870240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18871575000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18874120000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18875000000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18876000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18876880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18877480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18915255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18915960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18916455000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18917160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18918495000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18919245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18919875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18920655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18921435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18923240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18923240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18923240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18923240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18924040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18925540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18925540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18925540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18925540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18926340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18928500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18928500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18928500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18928500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18929300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18930075000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18930860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18931660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18932955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18933740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18936135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18936840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18937335000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18938040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18939375000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18940125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18940755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18941535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18942315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18944120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18944120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18944120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18944120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18944920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18946420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18946420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18946420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18946420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18947220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18949380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18949380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18949380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18949380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18950180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18950955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18951740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18952540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18953835000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18954620000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18957015000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18957720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18958215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18958920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18960255000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18961005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18961635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18962415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18963195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18965000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18965000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18965000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18965000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18965800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18967300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18967300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18967300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18967300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18968100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18970260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18970260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18970260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18970260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18971060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18971835000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18972620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18973420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18974715000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18975500000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18977740000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18977940000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18978220000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18979880000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18980080000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18980220000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18980360000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18981020000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18981240000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18981400000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18981560000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18985065000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18985480000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18985560000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18985940000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18987525000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18989020000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18990020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18990380000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18995160000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18995540000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18997440000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18997820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 18999820000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19000180000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19002615000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19002975000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19003580000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19003960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19004320000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19004680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19005975000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19006360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19007080000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19007440000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19009815000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19010200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19010920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19011000000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19012060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19013080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19014240000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19014620000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19015000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19015660000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19016540000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19016920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19018320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19019560000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19019920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19021320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19022115000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19022500000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19023220000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19023580000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19024520000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19029225000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19029680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19030545000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19031000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19031775000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19032320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19033680000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19033860000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19034240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19034920000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19035380000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19036160000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19036340000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19036720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19037380000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19038720000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19039100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19039480000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19040385000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19040780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19041495000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19041825000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19042220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19042815000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19043000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19043380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19044040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19044707000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19044900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19045280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19045960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19046655000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19046840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19047220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19047880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19048455000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19048640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19049020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19049680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19050255000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19050440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19050820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19051480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19052385000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19052580000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19052960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19053640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19054335000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19054665000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19055060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19055655000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19055840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19056220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19056855000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19057040000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19057420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19058080000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19060035000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19060220000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19060600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19061260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19062165000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19062360000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19062740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19063420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19067715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19067985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19068255000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19068885000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19069185000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19069455000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19070115000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19070385000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19071075000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19071825000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19072155000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19072965000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19073235000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19074075000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19080765000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19081065000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19081425000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19081785000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19085475000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19104840000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19105840000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19110140000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19111000000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19111800000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19112840000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19114360000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19115160000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19121100000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19122000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19122900000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19124265000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19126820000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19127700000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19128700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19129560000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19130160000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19133340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19134315000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19134700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19135960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19136805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19137200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19138620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19140015000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19140400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19150060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19163415000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19163800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19164660000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19165040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19165500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19166400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19166780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19167160000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19167520000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19167960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19168485000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19168560000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19169680000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19170040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19170480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19172220000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19172600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19172980000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19173340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19173780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19174305000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19174380000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19177640000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19180470000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19182740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19185570000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19187620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19187980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19188060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19188820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19189180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19189260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19190020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19190380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19190460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19191220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19191580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19191660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19193620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19193980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19194060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19194820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19195180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19195260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19196020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19196380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19196460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19197220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19197580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19197660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19199620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19200640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19201000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19201080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19201840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19202860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19203220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19203300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19204060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19205080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19205440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19205520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19206280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19207300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19207660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19207740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19209700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19210720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19211355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19211420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19212160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19213180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19213815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19213880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19214620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19215640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19216275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19216340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19217080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19218100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19218735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19218800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19219245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19219575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19219905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19220235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19220565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19220895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19221225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19223540000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19224525000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19224920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19226200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19227045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19227440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19228860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19230255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19230640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19240300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19253655000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19254040000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19254900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19255280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19255740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19256640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19257020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19257400000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19257760000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19258200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19258725000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19258800000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19259920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19260280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19260720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19262460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19262840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19263220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19263580000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19264020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19264545000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19264620000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19267880000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19270710000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19272980000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19275810000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19277860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19278220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19278300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19279060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19279420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19279500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19280260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19280620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19280700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19281460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19281820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19281900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19283860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19284220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19284300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19285060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19285420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19285500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19286260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19286620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19286700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19287460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19287820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19287900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19289860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19290880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19291240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19291320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19292080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19293100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19293460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19293540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19294300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19295320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19295680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19295760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19296520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19297540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19297900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19297980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19299940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19300960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19301595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19301660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19302400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19303420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19304055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19304120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19304860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19305880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19306515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19306580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19307320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19308340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19308975000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19309040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19309485000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19309815000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19310145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19310475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19310805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19311135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19311465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19313780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19314765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19315160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19316440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19317285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19317680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19319100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19320495000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19320880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19330540000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19343895000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19344280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19345140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19345520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19345980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19346880000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19347260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19347640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19348000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19348440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19348965000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19349040000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19350160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19350520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19350960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19352700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19353080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19353460000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19353820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19354260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19354785000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19354860000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19358120000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19360950000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19363220000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19366050000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19368100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19368460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19368540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19369300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19369660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19369740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19370500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19370860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19370940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19371700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19372060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19372140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19374100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19374460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19374540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19375300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19375660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19375740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19376500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19376860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19376940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19377700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19378060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19378140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19380100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19381120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19381480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19381560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19382320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19383340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19383700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19383780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19384540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19385560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19385920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19386000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19386760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19387780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19388140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19388220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19390180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19391200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19391835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19391900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19392640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19393660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19394295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19394360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19395100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19396120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19396755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19396820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19397560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19398580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19399215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19399280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19399725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19400055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19400385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19400715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19401045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19401375000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19401705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19404020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19405005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19405400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19406680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19407525000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19407920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19409340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19410735000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19411120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19420780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19434135000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19434520000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19435380000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19435760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19436220000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19437120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19437500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19437880000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19438240000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19438680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19439205000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19439280000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19440400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19440760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19441200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19442940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19443320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19443700000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19444060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19444500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19445025000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19445100000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19448360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19451190000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19453460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19456290000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19458340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19458700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19458780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19459540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19459900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19459980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19460740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19461100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19461180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19461940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19462300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19462380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19464340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19464700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19464780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19465540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19465900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19465980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19466740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19467100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19467180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19467940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19468300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19468380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19470340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19471360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19471720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19471800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19472560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19473580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19473940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19474020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19474780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19475800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19476160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19476240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19477000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19478020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19478380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19478460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19480420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19481440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19482075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19482140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19482880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19483900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19484535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19484600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19485340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19486360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19486995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19487060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19487800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19488820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19489455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19489520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19489965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19490295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19490625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19490955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19491285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19491615000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19491945000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19494525000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19495275000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19495660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19496235000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19496955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19497340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19497915000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19498635000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19499020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19499685000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19500435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19500820000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19501785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19502535000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19502920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19503885000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19504635000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19505020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19506405000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19507155000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19507540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19508925000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19509675000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19510060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19510965000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19511360000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19513845000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19514595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19514980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19526660000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19535140000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19553200000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19556460000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19557225000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19567700000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19576540000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19577625000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19578585000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19579020000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19579320000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19579620000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19580355000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19581015000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19581675000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19583720000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19584020000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19584765000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19585425000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19587075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19587255000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19587465000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19587675000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19587855000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19588065000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19588275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19588455000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19588635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19588815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19589025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19589235000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19589445000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19590135000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19590520000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19595505000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19598685000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19600400000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19605680000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19608630000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19646205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19646680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19647105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19647560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19648755000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19649445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19650135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19650825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19651545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19653140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19653140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19653140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19653140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19653800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19655120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19655120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19655120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19655120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19655780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19657460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19657460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19657460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19657460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19658120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19658895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19659540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19660200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19661595000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19662240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19664745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19665220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19665645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19666100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19667295000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19667985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19668675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19669365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19670085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19671680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19671680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19671680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19671680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19672340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19673660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19673660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19673660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19673660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19674320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19676000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19676000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19676000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19676000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19676660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19677435000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19678080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19678740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19680135000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19680780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19683285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19683760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19684185000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19684640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19685835000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19686525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19687215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19687905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19688625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19690220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19690220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19690220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19690220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19690880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19692200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19692200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19692200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19692200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19692860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19694540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19694540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19694540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19694540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19695200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19695975000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19696620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19697280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19698675000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19699320000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19701780000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19702000000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19702280000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19704100000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19704320000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19704460000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19704600000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19705320000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19705560000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19705720000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19705880000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19709415000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19709880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19709960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19710360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19712055000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19713700000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19714780000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19715160000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19719200000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19719600000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19721220000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19721620000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19723560000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19723960000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19726245000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19726515000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19727000000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19727400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19727800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19728180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19729485000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19729900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19730680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19731060000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19733385000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19733800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19734580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19734660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19735780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19736880000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19737940000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19738320000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19738720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19739440000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19740240000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19740640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19741860000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19742900000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19743300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19744520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19745295000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19745700000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19746480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19746880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19747900000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19752435000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19752900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19753695000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19754160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19754865000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19755420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19756680000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19756860000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19757260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19757980000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19758480000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19759120000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19759280000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19759680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19760400000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19761660000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19762060000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19762440000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19763325000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19763740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19764465000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19764795000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19765200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19765815000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19766000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19766400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19767120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19767737000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19767920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19768320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19769040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19769775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19769960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19770360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19771080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19771695000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19771880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19772280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19773000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19773615000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19773800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19774200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19774920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19775805000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19776000000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19776400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19777120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19777845000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19778175000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19778580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19779195000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19779380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19779780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19780365000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19780560000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19780960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19781680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19783815000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19784000000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19784400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19785120000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19786005000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19786200000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19786600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19787320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19791945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19792125000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19792305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19792875000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19793085000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19793265000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19793835000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19794015000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19794585000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19795275000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19795485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19796205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19796385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19797105000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19804965000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19805175000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19805415000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19805655000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19807545000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19824080000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19824960000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19828960000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19829700000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19830360000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19831160000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19832480000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19833140000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19838360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19839320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19840280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19841655000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19843460000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19844260000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19845280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19846180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19846780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19884315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19884960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19885395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19886060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19887285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19888005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19888695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19889415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19890105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19891700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19891700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19891700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19891700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19892360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19893680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19893680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19893680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19893680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19894340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19896020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19896020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19896020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19896020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19896900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19897695000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19898340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19899000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19900395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19901040000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19903575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19904240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19904685000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19905340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19906545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19907265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19907955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19908675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19909365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19910960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19910960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19910960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19910960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19911620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19912940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19912940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19912940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19912940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19913600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19915280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19915280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19915280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19915280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19916160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19916955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19917600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19918260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19919655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19920300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19922835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19923500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19923945000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19924600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19925805000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19926525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19927215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19927935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19928625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19930220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19930220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19930220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19930220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19930880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19932200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19932200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19932200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19932200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19932860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19934540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19934540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19934540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19934540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19935420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19936215000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19936860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19937520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19938915000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19939560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19942020000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19942240000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19942520000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19944340000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19944560000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19944700000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19944840000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19945560000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19945800000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19945960000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19946120000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19949655000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19950120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19950200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19950600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19952295000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19953940000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19955020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19955400000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19959620000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19960020000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19961640000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19962040000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19963980000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19964380000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19966695000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19966995000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19967640000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19968040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19968420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19968820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19970145000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19970560000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19971340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19971720000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19974075000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19974480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19975260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19975340000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19976460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19977600000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19978660000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19979040000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19979440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19980160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19980960000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19981360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19982580000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19983800000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19984200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19985420000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19986195000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19986600000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19987380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19987780000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19988800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19993365000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19993840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19994685000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19995160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19995915000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19996480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19997740000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19997900000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19998300000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19999020000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 19999520000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20000160000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20000340000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20000740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20001460000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20002720000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20003100000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20003500000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20004405000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20004820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20005545000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20005875000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20006280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20006895000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20007080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20007480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20008200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20008847000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20009040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20009440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20010160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20010885000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20011080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20011480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20012200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20012805000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20013000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20013400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20014120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20014725000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20014920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20015320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20016040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20016945000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20017140000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20017540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20018260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20018985000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20019315000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20019720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20020335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20020520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20020920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20021535000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20021720000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20022120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20022840000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20024985000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20025180000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20025580000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20026300000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20027205000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20027400000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20027800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20028520000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20033175000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20033385000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20033595000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20034195000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20034435000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20034645000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20035245000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20035455000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20036055000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20036775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20037015000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20037765000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20037975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20038725000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20046615000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20046855000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20047125000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20047395000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20049315000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20065880000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20066980000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20071120000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20071860000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20072520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20073320000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20074640000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20075300000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20080680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20081660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20082620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20083995000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20085980000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20086780000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20087800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20088700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20089300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20128305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20128920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20129385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20130020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20131275000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20132025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20132715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20133405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20134125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20135840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20135840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20135840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20135840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20136720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20138240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20138240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20138240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20138240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20139120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20140820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20140820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20140820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20140820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20141700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20142495000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20143140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20143800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20145195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20145840000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20148405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20149040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20149515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20150140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20151375000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20152125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20152815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20153505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20154225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20155940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20155940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20155940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20155940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20156820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20158340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20158340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20158340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20158340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20159220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20160920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20160920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20160920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20160920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20161800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20162595000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20163240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20163900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20165295000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20165940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20168505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20169140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20169615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20170240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20171475000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20172225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20172915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20173605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20174325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20176040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20176040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20176040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20176040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20176920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20178440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20178440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20178440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20178440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20179320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20181020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20181020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20181020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20181020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20181900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20182695000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20183340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20184000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20185395000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20186040000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20188500000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20188720000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20189000000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20190820000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20191040000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20191180000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20191320000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20192040000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20192280000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20192440000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20192600000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20196375000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20196840000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20196920000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20197320000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20199015000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20200660000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20201740000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20202120000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20206820000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20207220000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20209300000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20209680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20211860000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20212260000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20214825000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20215155000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20215760000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20216160000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20216560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20216940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20218305000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20218720000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20219500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20219880000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20222265000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20222680000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20223460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20223540000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20224660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20225760000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20227040000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20227440000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20227840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20228560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20229360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20229760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20230980000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20232200000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20232600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20234000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20234775000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20235180000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20235960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20236360000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20237380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20242455000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20242920000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20243775000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20244240000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20245005000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20245560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20247040000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20247200000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20247600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20248320000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20248820000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20249680000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20249840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20250240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20250960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20252440000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20252820000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20253220000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20254155000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20254560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20255295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20255625000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20256040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20256645000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20256840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20257240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20257960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20258627000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20258820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20259220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20259940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20260665000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20260860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20261260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20261980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20262585000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20262780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20263180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20263900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20264505000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20264700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20265100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20265820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20266755000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20266940000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20267340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20268060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20268795000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20269125000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20269540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20270145000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20270340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20270740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20271375000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20271560000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20271960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20272680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20274825000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20275020000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20275420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20276140000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20277045000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20277240000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20277640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20278360000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20283045000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20283285000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20283525000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20284155000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20284425000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20284665000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20285295000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20285535000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20286165000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20286915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20287185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20287965000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20288205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20288985000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20296905000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20297175000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20297475000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20297775000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20299725000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20317220000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20318320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20322460000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20323200000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20323860000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20324840000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20326340000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20327220000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20332800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20333780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20334740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20336145000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20338140000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20338940000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20339940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20340840000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20341440000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20380695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20381300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20381805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20382400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20383665000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20384445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20385135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20385855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20386545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20388260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20388260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20388260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20388260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20389140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20390660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20390660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20390660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20390660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20391540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20393420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20393420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20393420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20393420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20394300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20395095000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20395740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20396400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20397795000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20398440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20401035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20401640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20402145000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20402740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20404005000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20404785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20405475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20406195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20406885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20408600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20408600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20408600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20408600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20409480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20411000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20411000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20411000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20411000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20411880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20413760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20413760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20413760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20413760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20414640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20415435000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20416080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20416740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20418135000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20418780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20421375000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20421980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20422485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20423080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20424345000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20425125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20425815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20426535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20427225000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20428940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20428940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20428940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20428940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20429820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20431340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20431340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20431340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20431340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20432220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20434100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20434100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20434100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20434100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20434980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20435775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20436420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20437080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20438475000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20439120000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20441580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20441800000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20442080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20443900000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20444120000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20444260000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20444400000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20445120000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20445360000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20445520000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20445680000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20449455000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20449920000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20450000000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20450400000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20452095000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20453740000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20454820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20455200000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20459900000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20460300000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20462380000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20462760000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20464940000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20465340000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20467935000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20468295000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20468840000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20469240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20469640000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20470020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20471415000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20471820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20472600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20473000000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20475405000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20475820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20476600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20476680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20477800000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20478900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20480180000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20480580000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20480980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20481700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20482500000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20482900000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20484300000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20485520000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20485920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20487320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20488095000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20488500000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20489280000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20489680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20490700000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20495805000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20496280000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20497185000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20497660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20498475000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20499040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20500520000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20500700000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20501100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20501820000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20502320000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20503180000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20503340000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20503740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20504460000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20505940000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20506320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20506720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20507685000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20508100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20508825000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20509155000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20509560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20510175000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20510360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20510760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20511480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20512187000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20512380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20512780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20513500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20514225000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20514420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20514820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20515540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20516145000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20516340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20516740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20517460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20518065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20518260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20518660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20519380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20520345000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20520540000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20520940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20521660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20522385000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20522715000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20523120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20523735000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20523920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20524320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20524995000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20525180000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20525580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20526300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20528445000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20528640000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20529040000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20529760000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20530665000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20530860000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20531260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20531980000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20536695000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20536965000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20537235000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20537895000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20538195000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20538465000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20539125000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20539395000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20540055000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20540835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20541135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20541945000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20542215000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20543025000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20550975000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20551275000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20551605000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20551935000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20553915000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20573240000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20574340000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20578700000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20579580000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20580460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20581440000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20582960000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20583840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20589420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20590400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20591360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20592795000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20594960000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20595940000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20596960000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20597860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20598460000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20601840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20602485000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20602900000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20604100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20604675000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20605080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20606340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20607135000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20607540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20611760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20619735000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20620140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20621000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20621400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20621880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20622740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20623140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20623540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20623920000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20624400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20624985000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20625060000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20626000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20626380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20626860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20628020000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20628420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20628820000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20629200000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20629680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20630265000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20630340000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20633460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20636100000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20638140000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20640780000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20642940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20643340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20643420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20644140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20644540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20644620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20645340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20645740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20645820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20646540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20646940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20647020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20649060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20649460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20649540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20650260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20650660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20650740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20651460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20651860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20651940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20652660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20653060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20653140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20655180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20656300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20656680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20656760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20657460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20658580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20658960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20659040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20659740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20660860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20661240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20661320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20662020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20663140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20663520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20663600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20665620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20666740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20667435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20667500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20668200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20669320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20670015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20670080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20670780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20671900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20672595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20672660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20673360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20674480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20675175000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20675240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20675685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20676015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20676345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20676675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20677005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20677335000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20677665000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20680140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20680785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20681200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20682400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20682975000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20683380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20684640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20685435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20685840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20690060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20698035000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20698440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20699300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20699700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20700180000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20701040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20701440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20701840000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20702220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20702700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20703285000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20703360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20704300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20704680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20705160000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20706320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20706720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20707120000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20707500000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20707980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20708565000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20708640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20711760000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20714400000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20716440000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20719080000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20721240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20721640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20721720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20722440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20722840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20722920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20723640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20724040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20724120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20724840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20725240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20725320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20727360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20727760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20727840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20728560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20728960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20729040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20729760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20730160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20730240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20730960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20731360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20731440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20733480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20734600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20734980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20735060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20735760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20736880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20737260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20737340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20738040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20739160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20739540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20739620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20900520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20901640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20902335000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20902400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20903100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20904220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20906800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20907495000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20907560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20908260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20909380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20910075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20910140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20910585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20910915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20911245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20911575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20911905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20912235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20912565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20915295000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20916075000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20916480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20917005000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20917815000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20918220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20918745000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20919555000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20919960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20920545000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20921355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20921760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20922405000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20923215000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20923620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20924295000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20925075000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20925480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20926275000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20927055000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20927460000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20928285000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20929095000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20929500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20930115000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20930520000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20933145000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20933955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20934360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20940760000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20943920000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20950660000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20954100000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20954805000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20959900000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20963180000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20963955000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20964585000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20964960000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20965200000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20965440000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20966085000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20966655000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20967225000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20969400000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20969640000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20970285000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20970855000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20972655000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20972835000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20973045000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20973255000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20973435000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20973645000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20973855000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20974035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20974215000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20974395000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20974605000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20974815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20975025000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20975745000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20976160000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20981505000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20984445000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20985720000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20991020000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 20993850000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21028185000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21028580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21028995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21029380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21030765000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21031395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21031935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21032505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21033105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21034620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21034620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21034620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21034620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21035260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21036680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21036680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21036680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21036680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21037320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21040340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21040340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21040340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21040340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21040980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21041745000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21042380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21043020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21044265000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21044900000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21046965000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21047360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21047775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21048160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21049545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21050175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21050715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21051285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21051885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21053400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21053400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21053400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21053400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21054040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21055460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21055460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21055460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21055460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21056100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21059120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21059120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21059120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21059120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21059760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21060525000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21061160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21061800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21063045000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21063680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21065745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21066140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21066555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21066940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21068325000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21068955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21069495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21070065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21070665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21072180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21072180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21072180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21072180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21072820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21074240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21074240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21074240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21074240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21074880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21077900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21078540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21079305000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21079940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21080580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21081825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21082460000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21084360000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21084520000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21084840000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21086200000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21086360000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21086520000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21086680000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21087220000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21087400000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21087580000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21087760000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21090855000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21091260000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21091340000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21091680000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21093045000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21094420000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21095320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21095640000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21099840000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21100180000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21101720000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21102060000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21103860000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21104200000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21106215000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21106455000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21106860000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21107200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21107520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21107860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21108885000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21109240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21109900000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21110220000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21112455000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21112800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21113460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21113540000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21114480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21115440000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21116420000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21116760000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21117100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21117700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21118500000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21118840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21120220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21121400000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21121740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21123020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21123765000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21124120000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21124780000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21125100000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21125940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21129915000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21130320000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21131055000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21131460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21132105000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21132600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21133720000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21133880000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21134220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21134820000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21135260000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21135880000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21136040000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21136380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21136980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21138100000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21138420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21138760000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21139485000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21139840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21140505000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21140835000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21141180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21141735000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21141920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21142260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21142860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21143387000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21143580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21143920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21144520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21145185000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21145380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21145720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21146320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21146865000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21147060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21147400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21148000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21148545000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21148740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21149080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21149680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21150405000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21150600000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21150940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21151540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21152205000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21152535000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21152880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21153435000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21153620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21153960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21154455000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21154640000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21154980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21155580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21157365000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21157560000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21157900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21158500000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21159285000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21159480000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21159820000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21160420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21164115000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21164265000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21164415000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21164895000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21165075000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21165225000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21165825000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21165975000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21166575000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21167085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21167385000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21168075000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21168225000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21169035000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21171915000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21172095000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21172425000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21172755000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21181455000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21198860000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21199660000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21204040000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21204780000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21205420000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21206520000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21207840000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21208480000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21215660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21216440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21217220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21218355000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21221600000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21222500000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21223440000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21224280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21224880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21259155000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21259680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21260115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21260640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21262035000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21262665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21263235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21263805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21264375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21265960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21265960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21265960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21265960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21266600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21268000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21268000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21268000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21268000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21268640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21271640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21271640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21271640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21271640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21272280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21273045000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21273680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21274320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21275565000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21276200000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21278295000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21278820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21279255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21279780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21281175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21281805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21282375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21282945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21283515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21285100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21285100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21285100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21285100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21285740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21287140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21287140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21287140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21287140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21287780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21290780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21290780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21290780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21290780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21291420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21292185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21292820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21293460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21294705000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21295340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21297435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21297960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21298395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21298920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21300315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21300945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21301515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21302085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21302655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21304240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21304240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21304240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21304240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21304880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21306280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21306280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21306280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21306280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21306920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21309920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21309920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21309920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21309920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21310560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21311325000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21311960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21312600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21313845000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21314480000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21316380000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21316540000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21316860000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21318220000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21318380000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21318540000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21318700000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21319240000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21319420000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21319600000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21319780000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21322875000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21323280000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21323360000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21323700000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21325065000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21326440000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21327340000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21327660000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21331860000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21332200000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21333740000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21334080000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21335880000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21336220000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21338265000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21338535000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21339040000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21339360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21339700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21340020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21341055000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21341400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21342060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21342400000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21344685000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21345040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21345700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21345780000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21346720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21347640000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21348620000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21348960000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21349300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21349900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21350700000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21351040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21352420000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21353600000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21353940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21355320000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21356085000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21356440000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21357100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21357420000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21358260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21362265000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21362680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21363435000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21363840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21364515000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21365020000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21366140000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21366320000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21366660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21367260000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21367700000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21368320000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21368480000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21368820000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21369420000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21370540000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21370860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21371200000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21371955000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21372300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21372975000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21373305000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21373660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21374205000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21374400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21374740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21375340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21375887000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21376080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21376420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21377020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21377685000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21377880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21378220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21378820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21379365000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21379560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21379900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21380500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21381045000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21381240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21381580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21382180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21382935000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21383120000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21383460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21384060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21384735000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21385065000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21385420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21385965000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21386160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21386500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21387015000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21387200000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21387540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21388140000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21389925000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21390120000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21390460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21391060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21391845000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21392040000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21392380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21392980000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21396705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21396885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21397065000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21397575000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21397785000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21397965000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21398595000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21398775000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21399405000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21399975000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21400305000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21401025000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21401205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21402045000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21404955000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21405165000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21405525000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21405885000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21414615000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21433480000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21434280000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21438820000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21439560000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21440200000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21441300000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21442720000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21443360000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21450540000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21451340000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21452120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21453285000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21456640000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21457640000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21458580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21459420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21460020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21494325000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21494820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21495285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21495780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21497205000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21497895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21498525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21499125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21499695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21501260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21501260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21501260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21501260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21501900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21503320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21503320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21503320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21503320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21503960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21507060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21507060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21507060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21507060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21507700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21508455000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21509080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21509720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21510945000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21511580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21513705000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21514200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21514665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21515160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21516585000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21517275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21517905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21518505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21519075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21520640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21520640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21520640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21520640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21521280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21522700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21522700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21522700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21522700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21523340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21526440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21526440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21526440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21526440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21527080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21527835000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21528460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21529100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21530325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21530960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21533085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21533580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21534045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21534540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21535965000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21536655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21537285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21537885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21538455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21540020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21540020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21540020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21540020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21540660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21542080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21542080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21542080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21542080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21542720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21545820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21545820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21545820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21545820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21546460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21547215000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21547840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21548480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21549705000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21550340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21552240000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21552400000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21552720000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21554080000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21554240000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21554400000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21554560000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21555100000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21555280000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21555460000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21555640000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21558735000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21559140000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21559220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21559560000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21560925000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21562300000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21563200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21563520000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21567820000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21568140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21569680000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21570000000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21571800000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21572140000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21574215000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21574515000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21574960000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21575280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21575620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21575940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21577005000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21577360000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21578020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21578340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21580695000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21581040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21581700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21581780000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21582720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21583680000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21584660000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21585000000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21585340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21585940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21586740000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21587080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21588460000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21589740000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21590080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21591460000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21592215000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21592560000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21593220000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21593560000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21594400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21598425000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21598840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21599625000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21600040000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21600735000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21601240000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21602360000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21602540000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21602880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21603480000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21603920000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21604540000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21604700000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21605040000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21605640000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21606760000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21607080000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21607420000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21608205000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21608560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21609225000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21609555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21609900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21610455000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21610640000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21610980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21611580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21612167000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21612360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21612700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21613300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21613965000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21614160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21614500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21615100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21615645000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21615840000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21616180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21616780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21617325000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21617520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21617860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21618460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21619245000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21619440000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21619780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21620380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21621045000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21621375000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21621720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21622275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21622460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21622800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21623355000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21623540000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21623880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21624480000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21626265000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21626460000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21626800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21627400000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21628185000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21628380000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21628720000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21629320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21633075000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21633285000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21633495000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21634035000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21634275000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21634485000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21635145000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21635355000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21636015000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21636585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21636945000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21637695000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21637905000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21638775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21641715000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21641955000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21642345000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21642735000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21651495000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21670400000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21671360000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21675900000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21676800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21677600000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21678700000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21680120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21680760000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21688140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21689040000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21689940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21691005000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21694560000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21695360000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21696300000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21697140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21697740000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21732075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21732540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21733035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21733500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21734955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21735645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21736305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21736995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21737655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21739300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21739300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21739300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21739300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21739940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21741340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21741340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21741340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21741340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21741980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21745080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21745080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21745080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21745080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21745720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21746475000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21747100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21747740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21748965000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21749600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21751755000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21752220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21752715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21753180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21754635000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21755325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21755985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21756675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21757335000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21758980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21758980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21758980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21758980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21759620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21761020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21761020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21761020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21761020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21761660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21764760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21764760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21764760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21764760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21765400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21766155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21766780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21767420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21768645000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21769280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21771435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21771900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21772395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21772860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21774315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21775005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21775665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21776355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21777015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21778660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21778660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21778660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21778660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21779300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21780700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21780700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21780700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21780700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21781340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21784440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21784440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21784440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21784440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21785080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21785835000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21786460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21787100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21788325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21788960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21790860000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21791020000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21791340000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21792700000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21792860000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21793020000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21793180000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21793720000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21793900000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21794080000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21794260000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21797355000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21797760000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21797840000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21798180000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21799545000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21800920000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21801820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21802140000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21806440000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21806760000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21808300000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21808620000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21810420000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21810760000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21812865000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21813195000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21813740000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21814080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21814420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21814740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21815835000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21816180000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21816840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21817180000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21819585000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21819940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21820600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21820680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21821620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21822540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21823520000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21823860000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21824200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21824800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21825700000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21826020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21827400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21828680000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21829020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21830400000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21831165000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21831520000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21832180000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21832500000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21833340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21837405000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21837820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21838635000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21839040000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21839775000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21840280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21841400000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21841580000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21841920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21842520000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21842960000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21843580000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21843740000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21844080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21844680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21845800000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21846120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21846460000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21847275000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21847620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21848295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21848625000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21848980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21849525000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21849720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21850060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21850660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21851267000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21851460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21851800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21852400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21853065000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21853260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21853600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21854200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21854745000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21854940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21855280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21855880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21856425000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21856620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21856960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21857560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21858375000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21858560000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21858900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21859500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21860175000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21860505000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21860860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21861405000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21861600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21861940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21862515000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21862700000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21863040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21863640000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21865425000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21865620000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21865960000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21866560000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21867345000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21867540000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21867880000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21868480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21872445000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21872685000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21872925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21873495000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21873765000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21874005000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21874695000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21874935000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21875625000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21876255000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21876645000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21877425000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21877665000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21878565000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21881535000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21881805000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21882225000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21882645000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21891435000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21910400000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21911360000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21915900000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21916800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21917600000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21918700000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21920220000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21920860000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21928260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21929160000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21930060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21931155000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21934800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21935700000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21936660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21937500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21938100000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21940820000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21941805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21942160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21943300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 21943965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22027935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22028280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22029440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22033620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22044980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22058685000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22059040000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22059780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22060120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22060520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22063340000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22064400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22064740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22068915000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22068980000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22071740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22074300000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22076220000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22078770000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22080600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22080940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22081020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22103560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22104135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22104200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22104840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22105780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22106355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22106420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22107060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22108000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22109415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22109745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22110075000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported 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*SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22113120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22114095000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22114440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22115600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22116285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22116640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22117960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22119435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22119780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22131140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22144845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22145200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22145940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22146280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22146680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22147560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22147900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22148220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22148560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22148960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22149435000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22149500000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22150560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22150900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22151300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22153200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22153540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22153860000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22154200000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22154600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22155075000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22155140000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22157900000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22160460000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22162380000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22164930000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22166760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22167100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22167180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22167840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22168180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22168260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22168920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22169260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22169340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22170000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22170340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22170420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22172160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22172500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22172580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22173240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22173580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22173660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22174320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22174660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22174740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22175400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22175740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22175820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22177560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22178500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22178820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22178900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22179540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22180480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22180800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22180880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22181520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22182460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22182780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22182860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22183500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22184440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22184760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22184840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22186560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22187500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22188075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22188140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22188780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22189720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22190295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22190360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22191000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22191940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22192515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22192580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22193220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22194160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22194735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22194800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22195245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22195575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22195905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22196235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22196565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22196895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22197225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22199280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22200255000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22200600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22201760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22202445000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22202800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22204120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22205595000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22205940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22217300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22231005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22231360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22232100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22232440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22232840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22233720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22234060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22234380000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22234720000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22235120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22235595000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22235660000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22236720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22237060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22237460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22239360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22239700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22240020000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22240360000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22240760000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22241235000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22241300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22244060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22246620000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22248540000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22251090000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22252920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22253260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22253340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22254000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22254340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22254420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22255080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22255420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22255500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22256160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22256500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22256580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22258320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22258660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22258740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22259400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22259740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22259820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22260480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22260820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22260900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22261560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22261900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22261980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22263720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22264660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22264980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22265060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22265700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22266640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22266960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22267040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22267680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22268620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22268940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22269020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22269660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22270600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22270920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22271000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22272720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22273660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22274235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22274300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22274940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22275880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22276455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22276520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22277160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22278100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22278675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22278740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22279380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22280320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22280895000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22280960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22281405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22281735000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22282065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22282395000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22282725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22283055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22283385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22285665000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22286355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22286700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22287195000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22287855000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22288200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22288695000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22289355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22289700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22290225000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22290915000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22291260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22292145000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22292835000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22293180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22294065000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22294755000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22295100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22296495000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22297155000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22297500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22298895000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22299555000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22299900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22300725000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22301080000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22303245000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22303935000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22304280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22317520000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22327520000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22348900000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22351860000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22352535000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22364600000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22375220000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22376325000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22377285000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22377735000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22378095000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22378455000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22379205000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22379865000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22380525000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22382415000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22382775000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22383525000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22384185000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22385685000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22385865000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22386075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22386285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22386465000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22386675000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22386885000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22387065000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22387245000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22387425000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22387635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22387845000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22388055000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22388655000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22389000000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22393485000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22396725000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22398560000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22403500000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22406190000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22441485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22441980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22442385000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22442880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22444215000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22444815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22445325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22445925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22446495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22448020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22448020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22448020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22448020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22448740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22450060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22450060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22450060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22450060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22450780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22453420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22453420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22453420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22453420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22454140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22454925000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22455640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22456360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22457625000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22458340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22460445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22460940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22461345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22461840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22463175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22463775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22464285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22464885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22465455000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22466980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22466980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22466980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22466980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22467700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22469020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22469020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22469020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22469020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22469740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22472380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22472380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22472380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22472380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22473100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22473885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22474600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22475320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22476585000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22477300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22479405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22479900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22480305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22480800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22482135000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22482735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22483245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22483845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22484415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22485940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22485940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22485940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22485940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22486660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22487980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22487980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22487980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22487980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22488700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22491340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22491340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22491340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22491340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22492060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22492845000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22493560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22494280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22495545000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22496260000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22498260000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22498440000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22498760000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22500280000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22500460000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22500620000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22500780000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22501380000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22501580000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22501760000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22501940000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22505175000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22505600000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22505680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22506020000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22507485000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22508960000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22509920000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22510260000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22514600000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22514960000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22516480000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22516820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22518720000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22519080000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22521225000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22521465000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22521980000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22522340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22522700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22523060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22524165000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22524540000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22525260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22525620000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22527795000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22528160000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22528880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22528960000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22529940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22530920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22531820000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22532180000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22532540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22533180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22533880000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22534220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22535600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22536780000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22537140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22538380000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22539165000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22539540000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22540260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22540620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22541480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22545705000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22546140000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22546875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22547300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22547955000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22548480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22549500000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22549680000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22550040000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22550660000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22551120000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22551820000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22551980000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22552340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22552980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22554000000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22554360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22554720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22555455000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22555820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22556505000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22556835000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22557200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22557765000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22557960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22558320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22558940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22559477000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22559660000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22560020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22560660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22561335000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22561520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22561880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22562520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22563075000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22563260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22563620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22564260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22564815000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22565000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22565360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22566000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22566735000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22566920000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22567280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22567920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22568595000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22568925000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22569300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22569855000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22570040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22570400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22570905000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22571100000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22571460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22572080000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22573905000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22574100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22574460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22575080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22575945000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22576140000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22576500000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22577120000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22580985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22581135000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22581285000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22581795000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22581975000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22582125000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22582725000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22582875000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22583475000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22584045000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22584315000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22585005000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22585155000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22585935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22590045000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22590225000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22590525000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22590825000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22597815000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22615460000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22616180000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22620520000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22621280000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22622000000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22622940000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22624240000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22624960000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22631620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22632400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22633180000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22634415000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22637260000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22638200000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22639180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22640040000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22640640000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22676235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22676700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22677135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22677600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22678965000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22679625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22680255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22680855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22681425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22683040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22683040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22683040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22683040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22683760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22685200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22685200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22685200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22685200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22685920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22688680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22688680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22688680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22688680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22689400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22690185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22690900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22691620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22692885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22693600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22695735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22696200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22696635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22697100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22698465000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22699125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22699755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22700355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22700925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22702540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22702540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22702540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22702540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22703260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22704700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22704700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22704700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22704700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22705420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22708180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22708180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22708180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22708180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22708900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22709685000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22710400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22711120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22712385000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22713100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22715235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22715700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22716135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22716600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22717965000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22718625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22719255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22719855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22720425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22722040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22722040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22722040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22722040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22722760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22724200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22724200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22724200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22724200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22724920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22727680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22727680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22727680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22727680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22728400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22729185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22729900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22730620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22731885000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22732600000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22734600000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22734780000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22735100000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22736620000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22736800000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22736960000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22737120000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22737720000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22737920000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22738100000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22738280000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22741515000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22741940000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22742020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22742360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22743825000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22745300000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22746260000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22746600000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22751060000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22751420000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22753140000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22753500000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22755380000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22755740000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22757955000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22758225000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22758680000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22759040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22759400000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22759760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22760895000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22761260000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22761980000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22762340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22764615000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22764980000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22765700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22765780000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22766760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22767740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22768820000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22769180000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22769540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22770180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22771000000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22771340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22772720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22773900000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22774260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22775620000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22776405000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22776780000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22777500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22777860000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22778720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22782975000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22783400000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22784175000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22784600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22785285000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22785800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22787040000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22787220000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22787580000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22788200000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22788660000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22789360000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22789520000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22789880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22790520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22791720000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22792080000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22792440000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22793205000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22793580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22794255000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22794585000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22794960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22795515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22795700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22796060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22796700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22797257000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22797440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22797800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22798440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22799115000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22799300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22799660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22800300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22800855000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22801040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22801400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22802040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22802595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22802780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22803140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22803780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22804545000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22804740000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22805100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22805720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22806405000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22806735000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22807100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22807665000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22807860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22808220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22808745000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22808940000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22809300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22809920000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22811745000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22811940000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22812300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22812920000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22813785000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22813980000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22814340000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22814960000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22818855000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22819035000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22819215000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22819755000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22819965000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22820145000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22820775000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22820955000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22821585000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22822185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22822485000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22823205000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22823385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22824195000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22828335000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22828545000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22828875000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22829205000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22836225000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22853840000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22854740000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22859080000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22859840000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22860560000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22861620000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22863040000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22863760000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22870540000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22871440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22872340000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22873605000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22876580000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22877520000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22878480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22879320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22879920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22915545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22915980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22916445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22916880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22918275000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22918935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22919565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22920165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22920735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22922320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22922320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22922320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22922320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22923040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22924480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22924480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22924480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22924480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22925200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22927960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22927960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22927960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22927960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22928680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22929465000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22930180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22930900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22932165000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22932880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22935045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22935480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22935945000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22936380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22937775000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22938435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22939065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22939665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22940235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22941820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22941820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22941820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22941820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22942540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22943980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22943980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22943980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22943980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22944700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22947460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22947460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22947460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22947460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22948180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22948965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22949680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22950400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22951665000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22952380000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22954545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22954980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22955445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22955880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22957275000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22957935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22958565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22959165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22959735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22961320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22961320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22961320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22961320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22962040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22963480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22963480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22963480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22963480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22964200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22966960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22966960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22966960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22966960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22967680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22968465000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22969180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22969900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22971165000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22971880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22973880000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22974060000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22974380000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22975900000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22976080000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22976240000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22976400000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22977000000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22977200000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22977380000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22977560000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22980795000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22981220000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22981300000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22981640000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22983105000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22984580000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22985540000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22985880000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22990340000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22990700000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22992420000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22992780000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22994660000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22995020000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22997265000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22997565000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22998140000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22998500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22998860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 22999220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23000385000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23000760000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23001480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23001840000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23004135000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23004500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23005220000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23005300000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23006280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23007260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23008340000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23008700000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23009060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23009700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23010520000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23010860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23012240000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23013420000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23013780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23015140000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23015925000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23016300000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23017020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23017380000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23018240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23022525000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23022960000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23023755000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23024180000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23024895000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23025420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23026620000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23026800000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23027160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23027780000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23028240000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23028940000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23029100000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23029460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23030100000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23031300000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23031660000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23032020000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23032815000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23033180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23033865000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23034195000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23034560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23035125000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23035320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23035680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23036300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23036897000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23037080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23037440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23038080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23038755000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23038940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23039300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23039940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23040495000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23040680000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23041040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23041680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23042235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23042420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23042780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23043420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23044215000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23044400000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23044760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23045400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23046075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23046405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23046780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23047335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23047520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23047880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23048445000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23048640000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23049000000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23049620000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23051445000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23051640000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23052000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23052620000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23053485000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23053680000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23054040000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23054660000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23058585000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23058795000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23059005000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23059575000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23059815000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23060025000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23060685000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23060895000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23061555000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23062185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23062515000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23063265000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23063475000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23064315000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23068485000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23068725000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23069085000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23069445000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23076495000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23094200000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23095100000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23099620000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23100380000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23101100000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23102160000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23103580000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23104300000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23111260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23112160000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23113060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23114235000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23117440000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23118260000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23119240000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23120100000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23120700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23156355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23156940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23157435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23158020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23159445000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23160165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23160795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23161515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23162205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23163880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23164600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23166040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23166040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23166040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23166040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23166760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23169520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23169520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23169520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23169520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23170240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23171025000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23171740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23172460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23173725000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23174440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23176635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23177220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23177715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23178300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23179725000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23180445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23181075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23181795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23182485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23184160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23184160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23184160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23184160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23184880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23186320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23186320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23186320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23186320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23187040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23189800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23189800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23189800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23189800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23190520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23191305000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23192020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23192740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23194005000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23194720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23196915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23197500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23197995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23198580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23200005000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23200725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23201355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23202075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23202765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23204440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23204440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23204440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23204440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23205160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23206600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23206600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23206600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23206600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23207320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23210080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23210080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23210080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23210080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23210800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23211585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23212300000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23213020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23214285000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23215000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23217000000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23217180000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23217500000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23219020000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23219200000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23219360000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23219520000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23220120000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23220320000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23220500000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23220680000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23223915000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23224340000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23224420000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23224760000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23226225000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23227700000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23228660000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23229000000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23233580000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23233940000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23235660000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23236020000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23237900000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23238260000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23240535000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23240865000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23241380000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23241740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23242100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23242460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23243655000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23244020000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23244740000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23245100000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23247495000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23247860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23248580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23248660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23249640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23250620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23251700000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23252060000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23252420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23253060000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23253880000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23254220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23255600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23256780000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23257140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23258500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23259285000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23259660000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23260380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23260740000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23261600000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23265915000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23266340000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23267175000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23267600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23268345000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23268860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23270100000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23270280000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23270640000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23271260000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23271720000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23272420000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23272580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23272940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23273580000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23274780000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23275140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23275500000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23276325000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23276700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23277375000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23277705000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23278080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23278635000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23278820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23279180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23279820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23280437000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23280620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23280980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23281620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23282295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23282480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23282840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23283480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23284035000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23284220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23284580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23285220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23285775000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23285960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23286320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23286960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23287785000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23287980000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23288340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23288960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23289645000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23289975000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23290340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23290905000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23291100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23291460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23292045000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23292240000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23292600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23293220000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23295045000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23295240000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23295600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23296220000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23297085000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23297280000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23297640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23298260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23302215000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23302455000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23302695000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23303295000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23303565000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23303805000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23304495000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23304735000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23305425000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23306085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23306445000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23307225000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23307465000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23308335000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23312535000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23312805000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23313195000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23313585000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23320665000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23340140000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23341040000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23345560000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23346480000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23347200000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23348260000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23349700000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23350420000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23357380000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23358280000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23359180000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23360385000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23363720000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23364540000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23365500000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23366340000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23366940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23369840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23370975000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23371340000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23372620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23373495000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23373860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23375340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23377065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23377440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23390680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23406645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23407020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23407820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23408180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23408620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23409560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23409920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23410280000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23410640000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23411080000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23411595000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23411660000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23412840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23413200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23413640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23415740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23416100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23416460000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23416820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23417260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23417775000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23417840000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23420940000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23423670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23425920000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23428650000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23430620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23430980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23431060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23431760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23432120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23432200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23432900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23433260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23433340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23434040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23434400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23434480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23436320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23436680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23436760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23437460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23437820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23437900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23438600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23438960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23439040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23439740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23440100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23440180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23442020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23443020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23443380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23443460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23444180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23445180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23445540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23445620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23446340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23447340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23447700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23447780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23448500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23449500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23449860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23449940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23451800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23452800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23453415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23453480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23454200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23455200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23455815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23455880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23456600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23457600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23458215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23458280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23459000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23460000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23460615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23460680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23461125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23461455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23461785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23462115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23462445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23462775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23463105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23465240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23466375000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23466740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23468020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23468895000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23469260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23470740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23472465000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23472840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23486080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23502045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23502420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23503220000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23503580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23504020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23504960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23505320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23505680000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23506040000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23506480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23506995000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23507060000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23508240000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23508600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23509040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23511140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23511500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23511860000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23512220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23512660000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23513175000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23513240000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23516340000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23519070000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23521320000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23524050000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23526020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23526380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23526460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23527160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23527520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23527600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23528300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23528660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23528740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23529440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23529800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23529880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23531720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23532080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23532160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23532860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23533220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23533300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23534000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23534360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23534440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23535140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23535500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23535580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23537420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23538420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23538780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23538860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23539580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23540580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23540940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23541020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23541740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23542740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23543100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23543180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23543900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23544900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23545260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23545340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23547200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23548200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23548815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23548880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23549600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23550600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23551215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23551280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23552000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23553000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23553615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23553680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23554400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23555400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23556015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23556080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23556525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23556855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23557185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23557515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23557845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23558175000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23558505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23560640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23561775000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23562140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23563420000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23564295000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23564660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23566140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23567865000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23568240000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23581480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23597445000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23597820000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23598620000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23598980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23599420000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23600360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23600720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23601080000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23601440000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23601880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23602395000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23602460000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23603640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23604000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23604440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23606540000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23606900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23607260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23607620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23608060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23608575000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23608640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23611740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23614470000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23616720000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23619450000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23621420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23621780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23621860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23622560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23622920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23623000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23623700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23624060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23624140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23624840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23625200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23625280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23627120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23627480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23627560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23628260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23628620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23628700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23629400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23629760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23629840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23630540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23630900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23630980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23632820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23633820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23634180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23634260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23634980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23635980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23636340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23636420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23637140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23638140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23638500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23638580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23639300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23640300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23640660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23640740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23642600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23643600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23644215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23644280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23645000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23646000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23646615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23646680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23647400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23648400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23649015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23649080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23649800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23650800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23651415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23651480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23651925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23652255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23652585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23652915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23653245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23653575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23653905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23656040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23657175000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23657540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23658820000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23659695000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23660060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23661540000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23663265000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23663640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23676880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23692845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23693220000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23694020000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23694380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23694820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23695760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23696120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23696480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23696840000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23697280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23697795000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23697860000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23699040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23699400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23699840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23701940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23702300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23702660000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23703020000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23703460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23703975000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23704040000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23707140000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23709870000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23712120000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23714850000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23716820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23717180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23717260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23717960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23718320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23718400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23719100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23719460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23719540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23720240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23720600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23720680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23722520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23722880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23722960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23723660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23724020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23724100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23724800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23725160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23725240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23725940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23726300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23726380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23728220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23729220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23729580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23729660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23730380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23731380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23731740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23731820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23732540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23733540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23733900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23733980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23734700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23735700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23736060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23736140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23738000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23739000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23739615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23739680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23740400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23741400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23742015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23742080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23742800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23743800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23744415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23744480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23745200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23746200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23746815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23746880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23747325000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23747655000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23747985000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23748315000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23748645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23748975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23749305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23751675000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23752365000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23752740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23753295000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23753985000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23754360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23754915000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23755605000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23755980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23756625000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23757345000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23757720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23758785000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23759505000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23759880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23760945000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23761665000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23762040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23763705000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23764425000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23764800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23766465000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23767185000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23767560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23768565000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23768940000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23771175000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23771865000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23772240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23787280000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23799160000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23824540000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23827520000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23828265000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23842240000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23854720000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23855955000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23857065000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23857500000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23857815000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23858145000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23858925000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23859615000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23860305000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23862200000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23862525000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23863305000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23863995000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23865495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23865675000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23865885000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23866095000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23866275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23866485000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23866695000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23866875000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23867055000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23867235000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23867445000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23867655000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23867865000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23868495000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23868860000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23873385000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23876655000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23878580000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23883520000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23886360000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23922645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23923040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23923455000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23923840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23925105000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23925735000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23926305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23926845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23927385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23928920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23928920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23928920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23928920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23929520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23930900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23930900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23930900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23930900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23931500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23933860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23933860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23933860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23933860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23934460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23935245000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23936040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23936840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23938185000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23938980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23941275000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23941680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23942085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23942480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23943765000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23944395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23944965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23945505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23946045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23947580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23947580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23947580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23947580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23948180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23949560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23949560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23949560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23949560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23950160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23952520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23952520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23952520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23952520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23953120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23953905000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23954700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23955500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23956845000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23957640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23959935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23960340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23960745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23961140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23962425000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23963055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23963625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23964165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23964705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23966240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23966240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23966240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23966240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23966840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23968220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23968220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23968220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23968220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23968820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23971180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23971180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23971180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23971180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23971780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23972565000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23973360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23974160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23975505000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23976300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23978520000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23978720000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23979040000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23980700000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23980900000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23981060000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23981220000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23981880000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23982100000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23982280000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23982460000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23985735000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23986180000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23986260000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23986640000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23988195000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23989720000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23990720000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23991080000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23995240000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23995600000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23997080000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23997460000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23999320000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 23999680000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24001755000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24001995000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24002440000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24002800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24003160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24003520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24004665000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24005060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24005800000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24006160000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24008385000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24008780000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24009520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24009600000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24010660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24011680000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24012640000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24013000000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24013360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24014020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24014820000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24015200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24016500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24017600000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24017980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24019260000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24020055000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24020440000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24021160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24021520000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24022460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24026625000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24027080000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24027855000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24028300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24028965000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24029500000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24030640000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24030800000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24031180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24031840000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24032300000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24032880000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24033060000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24033440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24034120000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24035260000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24035620000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24035980000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24036765000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24037160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24037875000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24038205000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24038600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24039195000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24039380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24039760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24040420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24040967000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24041160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24041540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24042220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24042915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24043100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24043480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24044140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24044715000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24044900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24045280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24045940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24046515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24046700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24047080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24047740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24048525000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24048720000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24049100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24049780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24050475000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24050805000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24051200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24051795000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24051980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24052360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24052875000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24053060000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24053440000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24054100000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24056055000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24056240000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24056620000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24057280000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24058125000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24058320000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24058700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24059380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24063585000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24063735000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24063885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24064425000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24064605000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24064755000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24065325000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24065475000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24066045000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24066645000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24066885000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24067575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24067725000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24068475000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24073845000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24074025000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24074295000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24074565000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24079845000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24096440000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24097240000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24101380000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24102160000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24102760000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24103700000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24105080000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24105680000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24111940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24112780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24113620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24114885000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24117400000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24118340000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24119340000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24120220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24120820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24157635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24158200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24158625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24159200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24160515000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24161205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24161775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24162435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24162975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24164480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24164480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24164480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24164480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24165080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24166460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24166460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24166460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24166460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24167060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24169420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24169420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24169420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24169420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24170220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24171015000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24171800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24172600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24173925000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24174720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24177045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24177620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24178065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24178620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24179925000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24180585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24181155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24181695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24182235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24183740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24183740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24183740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24183740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24184340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24185720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24185720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24185720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24185720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24186320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24188680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24188680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24188680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24188680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24189480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24190275000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24191060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24191860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24193185000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24193980000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24196305000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24196880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24197325000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24197880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24199185000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24199845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24200415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24200955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24201495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24203000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24203000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24203000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24203000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24203600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24204980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24204980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24204980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24204980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24205580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24207940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24207940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24207940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24207940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24208740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24209535000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24210320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24211120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24212445000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24213240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24215460000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24215660000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24215980000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24217640000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24217840000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24218000000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24218160000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24218820000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24219040000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24219220000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24219400000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24222675000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24223120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24223200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24223580000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24225135000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24226660000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24227660000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24228020000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24232400000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24232780000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24234480000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24234860000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24236740000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24237100000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24239205000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24239475000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24240060000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24240440000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24240820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24241180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24242355000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24242740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24243460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24243820000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24246105000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24246500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24247240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24247320000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24248380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24249400000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24250360000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24250720000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24251080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24251740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24252540000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24252920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24254220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24255320000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24255700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24256980000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24257775000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24258160000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24258880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24259240000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24260180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24264585000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24265040000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24265845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24266300000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24267015000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24267560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24268720000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24268880000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24269260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24269920000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24270380000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24270960000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24271140000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24271520000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24272200000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24273340000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24273700000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24274060000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24274875000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24275260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24275955000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24276285000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24276680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24277275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24277460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24277840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24278500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24279077000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24279260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24279640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24280300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24280995000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24281180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24281560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24282220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24282795000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24282980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24283360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24284020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24284595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24284780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24285160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24285820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24286635000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24286820000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24287200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24287860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24288555000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24288885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24289280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24289875000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24290060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24290440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24290985000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24291180000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24291560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24292240000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24294195000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24294380000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24294760000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24295420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24296265000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24296460000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24296840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24297520000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24301755000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24301935000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24302115000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24302655000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24302865000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24303045000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24303675000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24303855000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24304455000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24305085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24305355000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24306075000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24306255000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24307035000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24312435000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24312645000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24312945000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24313245000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24318555000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24335280000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24336080000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24340420000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24341200000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24341800000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24342740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24344120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24344720000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24350980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24351820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24352660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24353955000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24356600000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24357540000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24358540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24359400000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24360000000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24397545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24398080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24398535000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24399080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24400425000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24401115000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24401685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24402375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24403065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24404660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24404660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24404660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24404660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24405460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24406820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24406820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24406820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24406820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24407620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24409960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24409960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24409960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24409960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24410760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24411555000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24412340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24413140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24414465000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24415260000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24417615000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24418160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24418635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24419160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24420495000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24421215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24421905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24422595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24423285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24424880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24424880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24424880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24424880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24425680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24427040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24427040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24427040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24427040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24427840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24430180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24430180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24430180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24430180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24430980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24431775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24432560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24433360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24434685000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24435480000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24437835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24438380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24438855000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24439380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24440715000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24441435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24442125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24442815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24443505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24445100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24445100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24445100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24445100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24445900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24447260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24447260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24447260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24447260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24448060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24450400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24450400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24450400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24450400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24451200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24451995000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24452780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24453580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24454905000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24455700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24457920000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24458120000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24458440000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24460100000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24460300000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24460460000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24460620000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24461280000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24461500000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24461680000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24461860000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24465375000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24465820000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24465900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24466280000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24467835000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24469360000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24470360000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24470720000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24475460000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24475840000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24477740000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24478120000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24480060000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24480440000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24482835000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24483135000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24483660000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24484040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24484420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24484780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24485985000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24486380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24487120000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24487480000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24489825000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24490220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24490960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24491040000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24492100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24493120000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24494280000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24494660000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24495040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24495700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24496500000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24496880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24498180000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24499420000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24499780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24501060000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24501855000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24502240000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24502960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24503320000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24504260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24508905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24509360000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24510195000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24510640000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24511365000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24511900000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24513240000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24513420000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24513800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24514480000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24514940000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24515720000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24515900000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24516280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24516940000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24518280000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24518660000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24519040000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24519885000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24520280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24520995000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24521325000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24521720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24522315000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24522500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24522880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24523540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24524147000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24524340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24524720000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24525400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24526095000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24526280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24526660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24527320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24527895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24528080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24528460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24529120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24529695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24529880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24530260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24530920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24531765000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24531960000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24532340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24533020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24533715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24534045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24534440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24535035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24535220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24535600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24536175000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24536360000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24536740000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24537400000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24539355000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24539540000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24539920000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24540580000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24541425000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24541620000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24542000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24542680000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24546945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24547155000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24547365000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24547965000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24548205000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24548415000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24549045000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24549255000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24549885000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24550545000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24550845000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24551595000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24551805000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24552615000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24558045000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24558285000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24558615000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24558945000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24564285000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24583100000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24584100000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24588440000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24589220000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24590020000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24590960000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24592340000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24593140000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24599380000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24600220000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24601060000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24602295000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24605080000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24605880000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24606880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24607740000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24608340000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24645915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24646420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24646905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24647420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24648795000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24649545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24650235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24650925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24651615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24653320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24653320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24653320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24653320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24654120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24655640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24655640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24655640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24655640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24656440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24658920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24658920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24658920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24658920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24659720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24660525000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24661320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24662120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24663465000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24664260000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24666645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24667160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24667665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24668160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24669525000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24670245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24670965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24671655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24672315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24674060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24674060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24674060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24674060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24674860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24676360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24676360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24676360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24676360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24677160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24679660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24679660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24679660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24679660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24680460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24681255000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24682040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24682840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24684165000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24684960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24687345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24687860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24688365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24688860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24690225000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24690945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24691665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24692355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24693015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24694760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24694760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24694760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24694760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24695560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24697060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24697060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24697060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24697060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24697860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24700360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24700360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24700360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24700360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24701160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24701955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24702740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24703540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24704865000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24705660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24707880000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24708080000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24708400000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24710060000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24710260000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24710420000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24710580000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24711240000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24711460000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24711640000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24711820000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24715335000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24715780000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24715860000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24716240000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24717795000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24719320000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24720320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24720680000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24725420000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24725800000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24727700000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24728080000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24730020000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24730400000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24732825000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24733155000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24733820000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24734200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24734560000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24734920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24736155000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24736540000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24737260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24737620000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24740025000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24740420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24741160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24741240000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24742300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24743320000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24744480000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24744860000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24745240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24745900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24746700000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24747080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24748520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24749760000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24750140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24751580000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24752385000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24752780000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24753520000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24753880000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24754820000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24759495000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24759940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24760785000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24761240000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24762015000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24762560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24763920000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24764100000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24764480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24765160000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24765620000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24766400000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24766580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24766960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24767620000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24768960000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24769340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24769720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24770595000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24770980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24771675000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24772005000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24772400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24772995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24773180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24773560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24774220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24774857000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24775040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24775420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24776080000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24776775000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24776960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24777340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24778000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24778575000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24778760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24779140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24779800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24780375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24780560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24780940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24781600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24782475000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24782660000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24783040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24783700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24784395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24784725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24785120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24785715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24785900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24786280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24786885000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24787080000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24787460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24788140000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24790095000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24790280000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24790660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24791320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24792165000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24792360000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24792740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24793420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24797715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24797955000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24798195000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24798795000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24799065000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24799305000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24799995000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24800235000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24800895000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24801585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24801915000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24802695000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24802935000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24803775000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24809235000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24809505000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24809865000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24810225000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24815595000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24834400000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24835400000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24839740000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24840520000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24841320000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24842400000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24843920000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24844720000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24851260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24852240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24853240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24854505000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24857440000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24858380000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24859380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24860260000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24860860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24863960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24864765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24865160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24866360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24866985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24867380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24868680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24869805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24870200000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24878000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24888585000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24888980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24889800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24890180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24890640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24891500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24891880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24892240000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24892600000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24893040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24893565000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24893640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24894640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24895000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24895440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24896960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24897340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24897700000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24898060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24898500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24899025000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24899100000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24902060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24904620000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24906620000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24909180000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24911200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24911560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24911640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24912340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24912700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24912780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24913480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24913840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24913920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24914620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24914980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24915060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24916960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24917320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24917400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24918100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24918460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24918540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24919240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24919600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24919680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24920380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24920740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24920820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24922720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24923740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24924100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24924180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24924880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24925900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24926260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24926340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24927040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24928060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24928420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24928500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24929200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24930220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24930580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24930660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24932560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24933580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24934215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24934280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24934960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24935980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24936615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24936680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24937360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24938380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24939015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24939080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24939760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24940780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24941415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24941480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24941925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24942255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24942585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24942915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24943245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24943575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24943905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24946160000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24946965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24947360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24948560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24949185000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24949580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24950880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24952005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24952400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24960200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24970785000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24971180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24972000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24972380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24972840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24973700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24974080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24974440000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24974800000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24975240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24975765000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24975840000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24976840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24977200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24977640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24979160000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24979540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24979900000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24980260000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24980700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24981225000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24981300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24984260000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24986820000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24988820000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24991380000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24993400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24993760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24993840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24994540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24994900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24994980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24995680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24996040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24996120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24996820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24997180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24997260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24999160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24999520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 24999600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25000300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25000660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25000740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25001440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25001800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25001880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25002580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25002940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25003020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25004920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25005940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25006300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25006380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25007080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25008100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25008460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25008540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25009240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25010260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25010620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25010700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25011400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25012420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25012780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25012860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25014760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25015780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25016415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25016480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25017160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25018180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25018815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25018880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25019560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25020580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25021215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25021280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25021960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25022980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25023615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25023680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25024125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25024455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25024785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25025115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25025445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25025775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25026105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25028360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25029165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25029560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25030760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25031385000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25031780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25033080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25034205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25034600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25042400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25052985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25053380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25054200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25054580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25055040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25055900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25056280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25056640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25057000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25057440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25057965000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25058040000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25059040000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25059400000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25059840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25061360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25061740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25062100000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25062460000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25062900000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25063425000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25063500000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25066460000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25069020000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25071020000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25073580000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25075600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25075960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25076040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25076740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25077100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25077180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25077880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25078240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25078320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25079020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25079380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25079460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25081360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25081720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25081800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25082500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25082860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25082940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25083640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25084000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25084080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25084780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25085140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25085220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25087120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25088140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25088500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25088580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25089280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25090300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25090660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25090740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25091440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25092460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25092820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25092900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25093600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25094620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25094980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25095060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25096960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25097980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25098615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25098680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25099360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25100380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25101015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25101080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25101760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25102780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25103415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25103480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25104160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25105180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25105815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25105880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25106325000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25106655000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25106985000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25107315000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25107645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25107975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25108305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25110560000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25111365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25111760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25112960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25113585000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25113980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25115280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25116405000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25116800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25124600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25135185000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25135580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25136400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25136780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25137240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25138100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25138480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25138840000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25139200000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25139640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25140165000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25140240000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25141240000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25141600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25142040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25143560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25143940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25144300000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25144660000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25145100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25145625000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25145700000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25148660000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25151220000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25153220000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25155780000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25157800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25158160000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25158240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25158940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25159300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25159380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25160080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25160440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25160520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25161220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25161580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25161660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25163560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25163920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25164000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25164700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25165060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25165140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25165840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25166200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25166280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25166980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25167340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25167420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25169320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25170340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25170700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25170780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25171480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25172500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25172860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25172940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25173640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25174660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25175020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25175100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25175800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25176820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25177180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25177260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25179160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25180180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25180815000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25180880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25181560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25182580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25183215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25183280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25183960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25184980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25185615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25185680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25186360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25187380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25188015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25188080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25188525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25188855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25189185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25189515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25189845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25190175000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25190505000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25192995000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25193715000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25194100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25194585000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25195335000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25195720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25196205000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25196955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25197340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25197885000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25198635000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25199020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25199775000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25200495000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25200880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25201635000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25202355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25202740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25203825000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25204575000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25204960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25206045000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25206795000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25207180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25207875000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25208260000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25210635000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25211355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25211740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25221520000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25228100000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25242160000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25245360000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25246035000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25254620000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25261580000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25262505000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25263285000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25263675000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25263975000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25264275000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25264965000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25265565000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25266165000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25268175000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25268475000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25269165000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25269765000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25271415000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25271595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25271805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272015000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272195000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272405000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272615000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272795000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25272975000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25273155000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25273365000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25273575000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25273785000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25274475000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25274860000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25279695000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25282695000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25284240000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25289140000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25291830000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25329405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25329880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25330275000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25330760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25331985000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25332675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25333305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25333905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25334535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25336160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25336160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25336160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25336160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25336820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25338200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25338200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25338200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25338200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25338860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25340880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25340880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25340880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25340880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25341540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25342365000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25343020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25343680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25345095000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25345740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25348245000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25348720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25349115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25349600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25350825000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25351515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25352145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25352745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25353375000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25355000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25355000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25355000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25355000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25355660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25357040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25357040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25357040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25357040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25357700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25359720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25359720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25359720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25359720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25360380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25361205000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25361860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25362520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25363935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25364580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25367085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25367560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25367955000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25368440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25369665000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25370355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25370985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25371585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25372215000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25373840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25373840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25373840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25373840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25374500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25375880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25375880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25375880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25375880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25376540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25378560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25378560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25378560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25378560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25379220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25380045000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25380700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25381360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25382775000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25383420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25385880000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25386100000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25386420000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25388260000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25388480000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25388640000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25388800000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25389520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25389760000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25389940000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25390120000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25393695000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25394160000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25394240000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25394640000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25396305000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25397920000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25399000000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25399380000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25403460000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25403860000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25405480000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25405860000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25407760000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25408140000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25410405000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25410645000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25411180000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25411560000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25411960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25412340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25413585000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25414000000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25414780000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25415160000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25417485000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25417900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25418680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25418760000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25419880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25420980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25422040000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25422420000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25422820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25423540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25424280000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25424680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25425980000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25427080000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25427460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25428760000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25429575000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25429980000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25430760000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25431160000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25432180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25436685000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25437160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25437945000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25438420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25439115000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25439680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25440940000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25441100000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25441500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25442220000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25442720000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25443360000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25443540000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25443940000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25444660000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25445920000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25446300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25446700000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25447545000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25447960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25448685000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25449015000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25449420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25450035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25450220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25450620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25451340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25451927000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25452120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25452520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25453240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25453965000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25454160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25454560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25455280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25455885000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25456080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25456480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25457200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25457805000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25458000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25458400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25459120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25459965000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25460160000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25460560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25461280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25462005000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25462335000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25462740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25463355000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25463540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25463940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25464495000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25464680000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25465080000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25465800000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25467945000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25468140000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25468540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25469260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25470165000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25470360000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25470760000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25471480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25475835000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25475985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25476135000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25476675000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25476855000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25477005000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25477575000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25477725000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25478295000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25478925000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25479135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25479825000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25479975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25480695000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25487295000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25487475000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25487715000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25487955000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25491525000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25508460000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25509340000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25513560000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25514360000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25515020000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25515920000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25517300000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25517960000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25523740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25524680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25525600000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25526955000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25529040000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25529940000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25530960000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25531860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25532460000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25569975000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25570420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25570845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25571300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25572555000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25573245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25573875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25574505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25575135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25576740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25576740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25576740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25576740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25577400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25578800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25578800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25578800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25578800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25579460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25581480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25581480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25581480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25581480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25582140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25582965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25583620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25584280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25585695000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25586340000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25588875000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25589320000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25589745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25590200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25591455000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25592145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25592775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25593405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25594035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25595640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25595640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25595640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25595640000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25596300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25597700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25597700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25597700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25597700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25598360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25600380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25600380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25600380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25600380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25601040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25601865000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25602520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25603180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25604595000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25605240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25607775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25608220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25608645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25609100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25610355000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25611045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25611675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25612305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25612935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25614540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25614540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25614540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25614540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25615200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25616600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25616600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25616600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25616600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25617260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25619280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25619280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25619280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25619280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25619940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25620765000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25621420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25622080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25623495000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25624140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25626600000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25626820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25627140000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25628980000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25629200000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25629360000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25629520000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25630240000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25630480000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25630660000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25630840000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25634415000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25634880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25634960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25635360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25637025000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25638640000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25639720000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25640100000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25644340000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25644720000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25646340000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25646740000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25648640000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25649040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25651335000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25651605000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25652080000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25652460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25652860000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25653240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25654515000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25654920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25655700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25656100000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25658445000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25658860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25659640000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25659720000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25660840000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25661940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25663000000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25663380000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25663780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25664500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25665240000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25665640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25666940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25668040000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25668420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25669720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25670535000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25670940000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25671720000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25672120000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25673140000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25677675000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25678140000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25678965000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25679440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25680165000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25680720000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25681980000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25682160000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25682560000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25683280000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25683780000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25684420000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25684580000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25684980000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25685700000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25686960000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25687360000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25687740000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25688625000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25689040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25689765000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25690095000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25690500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25691115000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25691300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25691700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25692420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25693037000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25693220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25693620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25694340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25695075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25695260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25695660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25696380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25696995000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25697180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25697580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25698300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25698915000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25699100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25699500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25700220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25701105000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25701300000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25701700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25702420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25703145000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25703475000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25703880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25704495000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25704680000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25705080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25705665000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25705860000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25706260000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25706980000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25709115000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25709300000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25709700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25710420000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25711365000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25711560000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25711960000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25712680000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25717305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25717485000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25717665000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25718235000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25718445000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25718625000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25719225000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25719405000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25720005000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25720695000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25720935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25721655000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25721835000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25722585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25729215000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25729425000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25729695000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25729965000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25733565000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25750520000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25751400000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25755620000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25756420000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25757080000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25757980000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25759380000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25760040000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25765840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25766780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25767700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25769085000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25771340000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25772240000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25773240000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25774140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25774740000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25812285000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25812920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25813395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25814020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25815315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25816035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25816665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25817295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25817925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25819500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25819500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25819500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25819500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25820160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25821560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25821560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25821560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25821560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25822220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25824240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25824240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25824240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25824240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25824900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25825725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25826380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25827040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25828455000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25829100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25831665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25832300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25832775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25833400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25834695000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25835415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25836045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25836675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25837305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25838880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25838880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25838880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25838880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25839540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25840940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25840940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25840940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25840940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25841600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25843620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25843620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25843620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25843620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25844280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25845105000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25845760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25846420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25847835000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25848480000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25851045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25851680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25852155000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25852780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25854075000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25854795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25855425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25856055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25856685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25858260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25858260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25858260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25858260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25858920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25860320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25860320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25860320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25860320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25860980000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25863000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25863000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25863000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25863000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25863660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25864485000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25865140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25865800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25867215000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25867860000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25870320000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25870540000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25870860000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25872700000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25872920000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25873080000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25873240000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25873960000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25874200000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25874380000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25874560000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25878135000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25878600000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25878680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25879080000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25880745000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25882360000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25883440000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25883820000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25888060000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25888440000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25890060000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25890460000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25892360000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25892760000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25895085000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25895385000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25896020000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25896420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25896820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25897200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25898505000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25898920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25899700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25900080000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25902465000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25902880000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25903660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25903740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25904860000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25905960000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25907020000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25907400000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25907800000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25908520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25909420000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25909800000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25911100000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25912200000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25912600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25913900000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25914705000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25915120000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25915900000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25916280000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25917300000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25921875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25922340000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25923195000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25923660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25924425000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25924980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25926240000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25926420000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25926820000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25927540000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25928040000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25928680000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25928840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25929240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25929960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25931220000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25931620000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25932000000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25932915000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25933320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25934055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25934385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25934800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25935405000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25935600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25936000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25936720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25937357000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25937540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25937940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25938660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25939395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25939580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25939980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25940700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25941315000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25941500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25941900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25942620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25943235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25943420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25943820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25944540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25945455000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25945640000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25946040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25946760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25947495000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25947825000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25948240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25948845000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25949040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25949440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25950045000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25950240000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25950640000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25951360000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25953495000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25953680000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25954080000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25954800000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25955745000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25955940000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25956340000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25957060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25961715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25961925000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25962135000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25962735000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25962975000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25963185000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25963815000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25964025000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25964655000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25965345000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25965615000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25966365000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25966575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25967355000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25974015000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25974255000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25974555000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25974855000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25978485000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25995440000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 25996320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26000540000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26001340000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26002000000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26002900000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26004300000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26004960000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26010760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26011700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26012620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26013975000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26016380000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26017280000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26018280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26019180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26019780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26058795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26059400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26059905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26060500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26061825000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26062605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26063235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26063835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26064465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26066000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26066000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26066000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26066000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26066880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26068280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26068280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26068280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26068280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26069160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26071200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26071200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26071200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26071200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26072080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26072895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26073540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26074200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26075625000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26076280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26078865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26079480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26079975000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26080580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26081895000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26082645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26083275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26083905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26084535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26086080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26086080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26086080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26086080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26086740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26088140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26088140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26088140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26088140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26089020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26091060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26091060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26091060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26091060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26091940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26092755000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26093400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26094060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26095485000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26096140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26098725000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26099340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26099835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26100440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26101755000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26102505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26103135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26103765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26104395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26105940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26105940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26105940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26105940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26106600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26108000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26108000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26108000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26108000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26108880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26110920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26110920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26110920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26110920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26111800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26112615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26113260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26113920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26115345000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26116000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26118460000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26118680000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26119000000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26120840000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26121060000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26121220000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26121380000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26122100000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26122340000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26122520000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26122700000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26126505000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26126940000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26127020000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26127420000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26129085000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26130700000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26131780000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26132160000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26136880000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26137260000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26139120000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26139520000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26141660000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26142060000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26144655000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26144985000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26145560000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26145960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26146360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26146740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26148075000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26148480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26149260000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26149660000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26152095000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26152500000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26153280000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26153360000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26154480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26155620000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26156900000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26157300000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26157700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26158420000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26159320000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26159700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26161000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26162260000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26162640000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26163940000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26164755000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26165160000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26165940000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26166340000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26167360000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26172435000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26172900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26173785000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26174260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26175045000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26175600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26176860000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26177040000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26177440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26178160000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26178660000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26179520000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26179700000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26180100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26180820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26182080000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26182480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26182860000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26183805000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26184220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26184945000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26185275000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26185680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26186295000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26186480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26186880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26187600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26188277000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26188460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26188860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26189580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26190315000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26190500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26190900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26191620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26192235000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26192420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26192820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26193540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26194155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26194340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26194740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26195460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26196405000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26196600000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26197000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26197720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26198445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26198775000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26199180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26199795000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26199980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26200380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26201025000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26201220000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26201620000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26202340000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26204475000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26204660000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26205060000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26205780000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26206725000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26206920000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26207320000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26208040000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26212725000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26212965000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26213205000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26213835000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26214105000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26214345000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26215005000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26215245000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26215905000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26216655000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26216955000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26217735000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26217975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26218785000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26225475000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26225745000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26226075000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26226405000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26230065000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26247040000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26248140000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26252360000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26253160000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26253820000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26254720000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26256120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26256780000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26262740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26263660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26264600000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26265945000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26268360000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26269260000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26270280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26271180000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26271780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26275220000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26276175000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26276580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26277940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26278755000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26279160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26280660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26282025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26282440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26292200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26305065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26305480000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26306400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26306800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26307260000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26308220000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26308620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26309020000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26309400000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26309880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26310465000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26310540000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26311720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26312100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26312580000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26314380000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26314780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26315160000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26315560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26316020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26316615000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26316680000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26320100000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26322840000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26325180000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26327910000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26330100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26330500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26330580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26331360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26331760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26331840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26332620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26333020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26333100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26333880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26334280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26334360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26336460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26336860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26336940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26337720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26338120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26338200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26338980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26339380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26339460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26340240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26340640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26340720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26342820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26343940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26344320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26344400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26345160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26346280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26346660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26346740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26347500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26348620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26349000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26349080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26349840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26350960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26351340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26351420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26353500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26354620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26355315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26355380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26356140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26357260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26357955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26358020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26358780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26359900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26360595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26360660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26361420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26362540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26363235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26363300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26363745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26364075000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26364405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26364735000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26365065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26365395000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26365725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26368260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26369205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26369620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26370980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26371815000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26372220000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26373720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26375085000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26375500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26385260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26398125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26398540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26399460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26399860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26400320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26401280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26401680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26402080000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26402460000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26402940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26403525000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26403600000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26404780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26405160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26405640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26407440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26407840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26408220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26408620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26409080000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26409675000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26409740000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26413160000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26415900000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26418240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26420970000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26423160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26423560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26423640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26424420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26424820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26424900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26425680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26426080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26426160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26426940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26427340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26427420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26429520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26429920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26430000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26430780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26431180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26431260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26432040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26432440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26432520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26433300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26433700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26433780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26435880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26437000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26437380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26437460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26438220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26439340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26439720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26439800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26440560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26441680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26442060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26442140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26442900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26444020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26444400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26444480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26446560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26447680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26448375000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26448440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26449200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26450320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26451015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26451080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26451840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26452960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26453655000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26453720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26454480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26455600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26456295000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26456360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26456805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26457135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26457465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26457795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26458125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26458455000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26458785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26461320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26462265000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26462680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26464040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26464875000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26465280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26466780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26468145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26468560000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26478320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26491185000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26491600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26492520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26492920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26493380000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26494340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26494740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26495140000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26495520000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26496000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26496585000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26496660000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26497840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26498220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26498700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26500500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26500900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26501280000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26501680000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26502140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26502735000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26502800000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26506220000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26508960000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26511300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26514030000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26516220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26516620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26516700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26517480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26517880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26517960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26518740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26519140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26519220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26520000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26520400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26520480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26522580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26522980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26523060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26523840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26524240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26524320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26525100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26525500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26525580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26526360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26526760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26526840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26528940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26530060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26530440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26530520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26531280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26532400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26532780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26532860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26533620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26534740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26535120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26535200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26535960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26537080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26537460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26537540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26539620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26540740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26541435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26541500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26542260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26543380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26544075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26544140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26544900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26546020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26546715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26546780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26547540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26548660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26549355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26549420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26549865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26550195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26550525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26550855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26551185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26551515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26551845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26554380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26555325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26555740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26557100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26557935000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26558340000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26559840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26561205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26561620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26571380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26584245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26584660000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26585580000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26585980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26586440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26587400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26587800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26588200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26588580000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26589060000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26589645000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26589720000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26590900000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26591280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26591760000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26593560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26593960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26594340000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26594740000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26595200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26595795000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26595860000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26599280000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26602020000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26604360000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26607090000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26609280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26609680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26609760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26610540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26610940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26611020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26611800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26612200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26612280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26613060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26613460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26613540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26615640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26616040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26616120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26616900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26617300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26617380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26618160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26618560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26618640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26619420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26619820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26619900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26622000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26623120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26623500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26623580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26624340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26625460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26625840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26625920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26626680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26627800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26628180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26628260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26629020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26630140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26630520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26630600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26632680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26633800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26634495000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26634560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26635320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26636440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26637135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26637200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26637960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26639080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26639775000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26639840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26640600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26641720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26642415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26642480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26642925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26643255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26643585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26643915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26644245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26644575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26644905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26647665000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26648475000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26648880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26649435000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26650215000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26650620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26651175000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26651955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26652360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26653005000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26653815000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26654220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26655165000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26655975000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26656380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26657325000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26658135000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26658540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26659905000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26660715000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26661120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26662485000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26663295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26663700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26664585000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26665000000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26667645000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26668455000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26668860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26680820000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26689300000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26707360000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26710860000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26711595000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26722240000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26731060000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26732115000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26733045000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26733480000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26733780000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26734080000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26734785000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26735415000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26736045000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26738280000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26738580000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26739285000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26739915000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26741715000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26741895000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26742105000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26742315000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26742495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26742705000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26742915000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26743095000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26743275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26743455000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26743665000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26743875000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26744085000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26744805000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26745220000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26750415000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26753415000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26755120000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26760040000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26762880000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26801685000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26802240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26802645000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26803200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26804385000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26805075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26805615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26806305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26806815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26808340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26808340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26808340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26808340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26809060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26810440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26810440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26810440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26810440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26811160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26812900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26812900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26812900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26812900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26813620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26814465000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26815180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26815900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26817345000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26818060000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26820585000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26821140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26821545000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26822100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26823285000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26823975000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26824515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26825205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26825715000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26827240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26827240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26827240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26827240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26827960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26829340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26829340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26829340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26829340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26830060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26831800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26831800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26831800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26831800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26832520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26833365000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26834080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26834800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26836245000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26836960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26839485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26840040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26840445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26841000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26842185000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26842875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26843415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26844105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26844615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26846140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26846140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26846140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26846140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26846860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26848240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26848240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26848240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26848240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26848960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26850700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26850700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26850700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26850700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26851420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26852265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26852980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26853700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26855145000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26855860000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26858400000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26858640000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26858960000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26860960000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26861200000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26861360000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26861520000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26862300000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26862560000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26862740000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26862920000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26866635000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26867120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26867200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26867600000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26869365000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26871080000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26872220000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26872620000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26876920000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26877320000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26879080000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26879480000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26881540000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26881940000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26884305000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26884545000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26885180000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26885600000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26886020000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26886440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26887785000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26888220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26889060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26889480000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26891835000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26892260000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26893100000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26893180000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26894340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26895500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26896640000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26897060000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26897480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26898240000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26899060000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26899460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26900720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26901780000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26902200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26903440000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26904285000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26904720000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26905560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26905980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26907020000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26911725000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26912220000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26913015000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26913500000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26914215000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26914800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26916120000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26916300000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26916720000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26917460000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26917980000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26918680000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26918840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26919260000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26920020000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26921340000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26921760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26922180000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26923035000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26923460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26924205000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26924535000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26924960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26925585000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26925780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26926200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26926940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26927537000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26927720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26928140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26928900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26929635000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26929820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26930240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26931000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26931615000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26931800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26932220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26932980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26933595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26933780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26934200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26934960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26935815000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26936000000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26936420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26937180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26937915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26938245000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26938680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26939295000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26939480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26939900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26940465000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26940660000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26941080000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26941820000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26944005000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26944200000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26944620000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26945360000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26946225000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26946420000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26946840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26947580000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26952105000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26952255000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26952405000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26952975000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26953155000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26953305000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26953875000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26954025000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26954595000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26955285000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26955465000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26956185000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26956335000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26957055000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26964885000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26965065000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26965275000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26965485000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26967345000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26983880000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26984840000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26988820000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26989480000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26990200000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26991020000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26992400000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26993120000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26998240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26999080000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 26999920000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27001365000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27003200000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27004020000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27005040000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27005940000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27006540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27045255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27045780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27046215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27046740000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27047955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27048645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27049365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27050055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27050745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27052420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27052420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27052420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27052420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27053140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27054520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27054520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27054520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27054520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27055240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27056980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27056980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27056980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27056980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27057700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27058545000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27059260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27059980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27061425000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27062140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27064695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27065220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27065655000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27066180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27067395000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27068085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27068805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27069495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27070185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27071860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27071860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27071860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27071860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27072580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27073960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27073960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27073960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27073960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27074680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27076420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27076420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27076420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27076420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27077140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27077985000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27078700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27079420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27080865000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27081580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27084135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27084660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27085095000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27085620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27086835000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27087525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27088245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27088935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27089625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27091300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27091300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27091300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27091300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27092020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27093400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27093400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27093400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27093400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27094120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27095860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27095860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27095860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27095860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27096580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27097425000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27098140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27098860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27100305000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27101020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27103560000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27103800000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27104120000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27106120000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27106360000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27106520000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27106680000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27107460000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27107720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27107900000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27108080000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27111795000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27112280000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27112360000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27112760000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27114525000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27116240000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27117380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27117780000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27122080000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27122480000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27124240000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27124640000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27126700000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27127100000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27129495000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27129765000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27130340000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27130760000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27131180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27131600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27132975000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27133400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27134240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27134660000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27137085000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27137520000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27138360000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27138440000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27139620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27140780000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27141920000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27142340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27142760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27143520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27144340000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27144740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27146000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27147060000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27147480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27148720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27149565000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27150000000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27150840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27151260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27152300000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27157035000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27157520000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27158355000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27158840000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27159585000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27160160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27161520000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27161700000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27162120000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27162860000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27163380000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27164080000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27164240000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27164660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27165420000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27166740000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27167160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27167580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27168465000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27168900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27169635000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27169965000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27170400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27171015000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27171200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27171620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27172380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27172997000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27173180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27173600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27174360000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27175095000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27175280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27175700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27176460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27177075000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27177260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27177680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27178440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27179055000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27179240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27179660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27180420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27181305000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27181500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27181920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27182660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27183405000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27183735000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27184160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27184785000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27184980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27185400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27185985000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27186180000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27186600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27187340000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27189525000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27189720000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27190140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27190880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27191745000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27191940000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27192360000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27193100000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27197655000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27197835000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27198015000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27198615000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27198825000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27199005000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27199605000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27199785000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27200385000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27201105000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27201315000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27202065000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27202245000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27202995000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27210855000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27211065000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27211305000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27211545000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27213435000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27230000000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27230960000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27234940000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27235760000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27236480000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27237300000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27238660000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27239380000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27244720000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27245740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27246760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27248205000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27250040000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27250860000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27251880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27252780000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27253380000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27292125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27292620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27293085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27293580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27294825000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27295575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27296295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27296985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27297675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27299320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27299320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27299320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27299320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27300040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27301420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27301420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27301420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27301420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27302140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27303880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27303880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27303880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27303880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27304600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27305445000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27306160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27306880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27308325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27309040000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27311625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27312120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27312585000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27313080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27314325000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27315075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27315795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27316485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27317175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27318820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27318820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27318820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27318820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27319540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27320920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27320920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27320920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27320920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27321640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27323380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27323380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27323380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27323380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27324100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27324945000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27325660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27326380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27327825000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27328540000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27331125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27331620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27332085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27332580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27333825000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27334575000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27335295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27335985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27336675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27338320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27338320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27338320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27338320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27339040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27340420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27340420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27340420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27340420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27341140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27342880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27342880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27342880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27342880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27343600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27344445000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27345160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27345880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27347325000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27348040000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27350580000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27350820000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27351140000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27353140000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27353380000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27353540000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27353700000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27354480000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27354740000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27354920000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27355100000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27358815000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27359300000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27359380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27359780000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27361545000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27363260000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27364400000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27364800000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27369280000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27369680000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27371440000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27371840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27373900000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27374300000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27376725000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27377025000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27377540000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27377960000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27378380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27378800000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27380205000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27380640000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27381480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27381900000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27384315000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27384740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27385580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27385660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27386820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27387980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27389120000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27389540000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27389960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27390720000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27391540000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27391940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27393200000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27394260000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27394680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27395920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27396765000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27397200000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27398040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27398460000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27399500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27404265000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27404760000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27405615000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27406100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27406875000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27407460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27408780000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27408960000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27409380000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27410120000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27410640000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27411340000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27411500000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27411920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27412680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27414000000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27414420000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27414840000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27415755000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27416180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27416925000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27417255000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27417680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27418305000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27418500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27418920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27419660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27420317000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27420500000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27420920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27421680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27422415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27422600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27423020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27423780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27424395000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27424580000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27425000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27425760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27426375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27426560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27426980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27427740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27428655000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27428840000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27429260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27430020000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27430755000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27431085000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27431520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27432135000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27432320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27432740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27433365000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27433560000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27433980000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27434720000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27436905000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27437100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27437520000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27438260000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27439125000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27439320000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27439740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27440480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27445305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27445515000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27445725000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27446355000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27446595000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27446805000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27447435000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27447645000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27448275000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27449025000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27449265000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27450045000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27450255000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27451035000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27458925000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27459165000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27459435000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27459705000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27461625000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27478220000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27479180000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27483400000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27484220000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27484940000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27485760000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27487120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27487840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27493300000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27494320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27495340000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27496785000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27498800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27499620000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27500640000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27501540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27502140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27540915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27541620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27542115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27542820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27544095000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27544845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27545565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27546255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27546945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27548560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27548560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27548560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27548560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27549280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27550660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27550660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27550660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27550660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27551380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27553120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27553120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27553120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27553120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27554080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27554925000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27555640000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27556360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27557805000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27558520000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27561135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27561840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27562335000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27563040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27564315000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27565065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27565785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27566475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27567165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27568780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27568780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27568780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27568780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27569500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27570880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27570880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27570880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27570880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27571600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27573340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27573340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27573340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27573340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27574300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27575145000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27575860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27576580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27578025000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27578740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27581355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27582060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27582555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27583260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27584535000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27585285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27586005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27586695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27587385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27589000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27589000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27589000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27589000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27589720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27591100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27591100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27591100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27591100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27591820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27593560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27593560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27593560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27593560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27594520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27595365000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27596080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27596800000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27598245000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27598960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27601500000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27601740000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27602060000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27604060000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27604300000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27604460000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27604620000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27605400000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27605660000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27605840000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27606020000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27609735000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27610220000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27610300000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27610700000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27612465000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27614180000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27615320000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27615720000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27620200000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27620600000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27622360000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27622760000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27624820000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27625220000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27627675000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27628005000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27628700000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27629120000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27629540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27629960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27631395000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27631820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27632660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27633080000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27635565000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27636000000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27636840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27636920000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27638100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27639260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27640400000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27640820000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27641240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27642000000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27642820000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27643220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27644660000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27645900000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27646320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27647560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27648405000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27648840000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27649680000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27650100000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27651140000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27655935000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27656420000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27657315000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27657800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27658605000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27659180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27660540000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27660720000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27661140000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27661880000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27662400000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27663100000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27663260000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27663680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27664440000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27665760000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27666180000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27666600000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27667545000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27667980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27668715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27669045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27669480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27670095000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27670280000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27670700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27671460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27672137000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27672320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27672740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27673500000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27674235000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27674420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27674840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27675600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27676215000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27676400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27676820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27677580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27678195000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27678380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27678800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27679560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27680505000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27680700000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27681120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27681860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27682605000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27682935000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27683360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27683985000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27684180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27684600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27685245000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27685440000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27685860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27686600000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27688785000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27688980000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27689400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27690140000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27691005000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27691200000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27691620000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27692360000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27697215000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27697455000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27697695000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27698355000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27698625000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27698865000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27699525000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27699765000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27700425000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27701205000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27701475000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27702285000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27702525000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27703335000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27711255000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27711525000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27711825000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27712125000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27714075000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27731600000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27732560000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27736780000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27737600000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27738320000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27739140000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27740500000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27741220000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27746680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27747700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27748720000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27750195000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27752200000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27753020000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27754060000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27754980000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27755580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27759080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27759705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27760140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27761360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27761925000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27762360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27763620000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27764385000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27764820000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27769040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27776505000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27776940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27777800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27778220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27778720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27779640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27780060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27780480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27780900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27781400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27781995000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27782060000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27783000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27783420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27783920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27785100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27785520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27785940000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27786360000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27786860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27787455000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27787520000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27790680000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27793230000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27795300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27797850000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27800060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27800480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27800560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27801260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27801680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27801760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27802460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27802880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27802960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27803660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27804080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27804160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27806240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27806660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27806740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27807440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27807860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27807940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27808640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27809060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27809140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27809840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27810260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27810340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27812420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27813600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27814020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27814100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27814820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27816000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27816420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27816500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27817220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27818400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27818820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27818900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27819620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27820800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27821220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27821300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27823400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27824580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27825315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27825380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27826100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27827280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27828015000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27828080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27828800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27829980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27830715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27830780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27831500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27832680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27833415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27833480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27833925000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27834255000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27834585000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27834915000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27835245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27835575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27835905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27838400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27839025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27839460000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27840680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27841245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27841680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27842940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27843705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27844140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27848360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27855825000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27856260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27857120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27857540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27858040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27858960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27859380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27859800000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27860220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27860720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27861315000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27861380000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27862320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27862740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27863240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27864420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27864840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27865260000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27865680000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27866180000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27866775000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27866840000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27870000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27872550000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27874620000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27877170000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27879380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27879800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27879880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27880580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27881000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27881080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27881780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27882200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27882280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27882980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27883400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27883480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27885560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27885980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27886060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27886760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27887180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27887260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27887960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27888380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27888460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27889160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27889580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27889660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27891740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27892920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27893340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27893420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27894140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27895320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27895740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27895820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27896540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27897720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27898140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27898220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27898940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27900120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27900540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27900620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27902720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27903900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27904635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27904700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27905420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27906600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27907335000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27907400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27908120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27909300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27910035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27910100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27910820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27912000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27912735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27912800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27913245000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27913575000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27913905000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27914235000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27914565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27914895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27915225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27917720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27918345000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27918780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27920000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27920565000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27921000000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27922260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27923025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27923460000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27927680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27935145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27935580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27936440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27936860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27937360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27938280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27938700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27939120000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27939540000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27940040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27940635000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27940700000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27941640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27942060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27942560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27943740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27944160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27944580000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27945000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27945500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27946095000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27946160000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27949320000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27951870000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27953940000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27956490000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27958700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27959120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27959200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27959900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27960320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27960400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27961100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27961520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27961600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27962300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27962720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27962800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27964880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27965300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27965380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27966080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27966500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27966580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27967280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27967700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27967780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27968480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27968900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27968980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27971060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27972240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27972660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27972740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27973460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27974640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27975060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27975140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27975860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27977040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27977460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27977540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27978260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27979440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27979860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27979940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27982040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27983220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27983955000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27984020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27984740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27985920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27986655000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27986720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27987440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27988620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27989355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27989420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27990140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27991320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27992055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27992120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27992565000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27992895000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27993225000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27993555000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27993885000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27994215000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27994545000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27997040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27997665000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27998100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27999320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 27999885000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28000320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28001580000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28002345000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28002780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28007000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28014465000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28014900000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28015760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28016180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28016680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28017600000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28018020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28018440000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28018860000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28019360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28019955000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28020020000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28020960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28021380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28021880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28023060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28023480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28023900000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28024320000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28024820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28025415000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28025480000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28028640000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28031190000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28033260000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28035810000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28038020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28038440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28038520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28039220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28039640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28039720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28040420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28040840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28040920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28041620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28042040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28042120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28044200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28044620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28044700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28045400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28045820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28045900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28046600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28047020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28047100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28047800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28048220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28048300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28050380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28051560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28051980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28052060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28052780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28053960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28054380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28054460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28055180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28056360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28056780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28056860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28057580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28058760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28059180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28059260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28061360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28062540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28063275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28063340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28064060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28065240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28065975000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28066040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28066760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28067940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28068675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28068740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28069460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28070640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28071375000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28071440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28071885000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28072215000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28072545000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28072875000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28073205000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28073535000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28073865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28076595000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28077405000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28077840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28078335000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28079145000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28079580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28080075000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28080885000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28081320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28081845000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28082685000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28083120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28083735000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28084545000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28084980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28085625000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28086465000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28086900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28087665000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28088505000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28088940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28089735000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28090545000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28090980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28091565000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28092000000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28094595000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28095405000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28095840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28102340000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28105520000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28112260000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28115840000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28116525000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28121660000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28124960000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28125705000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28126305000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28126680000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28126920000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28127160000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28127775000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28128315000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28128855000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28131020000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28131260000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28131885000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28132425000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28134255000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28134435000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28134645000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28134855000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135245000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135455000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28135995000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28136205000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28136415000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28136625000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28137375000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28137800000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28143045000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28145805000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28147040000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28151980000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28154670000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28189125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28189620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28190025000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28190520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28191885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28192545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28193085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28193685000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28194255000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28195920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28195920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28195920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28195920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28196460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28197900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28197900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28197900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28197900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28198440000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28201480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28201480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28201480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28201480000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28202200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28203015000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28203720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28204440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28205715000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28206420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28208505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28209000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28209405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28209900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28211265000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28211925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28212465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28213065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28213635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28215300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28215300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28215300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28215300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28215840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28217280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28217280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28217280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28217280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28217820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28220860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28220860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28220860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28220860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28221580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28222395000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28223100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28223820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28225095000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28225800000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28227885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28228380000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28228785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28229280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28230645000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28231305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28231845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28232445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28233015000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28234680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28234680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28234680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28234680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28235220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28236660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28236660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28236660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28236660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28237200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28240240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28240240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28240240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28240240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28240960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28241775000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28242480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28243200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28244475000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28245180000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28247160000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28247340000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28247700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28249200000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28249380000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28249560000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28249740000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28250340000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28250540000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28250740000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28250940000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28253955000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28254380000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28254460000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28254800000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28256235000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28257740000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28258700000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28259040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28263060000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28263420000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28264940000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28265300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28267040000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28267400000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28269375000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28269585000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28270100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28270460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28270820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28271180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28272255000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28272620000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28273340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28273700000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28275945000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28276320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28277040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28277120000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28278120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28279100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28280180000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28280540000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28280900000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28281540000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28282360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28282700000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28284020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28285220000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28285580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28286900000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28287705000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28288080000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28288800000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28289160000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28290020000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28293825000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28294260000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28294995000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28295420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28296075000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28296600000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28297620000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28297800000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28298160000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28298780000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28299240000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28299760000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28299920000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28300280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28300920000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28301940000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28302300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28302660000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28303365000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28303740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28304415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28304745000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28305120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28305675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28305860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28306220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28306860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28307357000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28307540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28307900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28308540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28309215000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28309400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28309760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28310400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28310955000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28311140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28311500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28312140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28312695000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28312880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28313240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28313880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28314585000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28314780000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28315140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28315760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28316445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28316775000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28317140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28317705000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28317900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28318260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28318725000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28318920000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28319280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28319900000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28321725000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28321920000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28322280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28322900000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28323705000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28323900000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28324260000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28324880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28328745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28328865000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28328985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28329465000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28329615000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28329735000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28330335000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28330455000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28331055000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28331565000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28331835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28332495000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28332615000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28333395000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28336275000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28336425000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28336725000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28337025000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28345695000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28363060000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28363780000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28368080000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28368900000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28369620000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28370740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28372200000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28372740000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28379980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28380820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28381660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28382835000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28386100000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28387020000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28387980000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28388820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28389420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28424655000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28425120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28425555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28426020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28427415000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28428045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28428585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28429185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28429755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28431420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28431420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28431420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28431420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28431960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28433400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28433400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28433400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28433400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28433940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28436980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28436980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28436980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28436980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28437700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28438515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28439220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28439940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28441215000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28441920000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28444035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28444500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28444935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28445400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28446795000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28447425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28447965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28448565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28449135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28450800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28450800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28450800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28450800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28451340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28452780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28452780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28452780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28452780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28453320000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28456360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28456360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28456360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28456360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28457080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28457895000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28458600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28459320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28460595000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28461300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28463415000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28463880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28464315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28464780000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28466175000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28466805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28467345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28467945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28468515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28470180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28470180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28470180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28470180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28470720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28472160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28472160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28472160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28472160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28472700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28475740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28475740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28475740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28475740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28476460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28477275000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28477980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28478700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28479975000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28480680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28482660000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28482840000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28483200000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28484700000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28484880000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28485060000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28485240000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28485840000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28486040000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28486240000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28486440000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28489455000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28489880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28489960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28490300000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28491735000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28493240000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28494200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28494540000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28498760000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28499120000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28500660000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28501020000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28502740000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28503080000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28505325000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28505565000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28506020000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28506380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28506740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28507100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28508205000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28508580000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28509300000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28509660000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28511925000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28512300000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28513020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28513100000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28514100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28515080000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28516160000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28516520000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28516880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28517520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28518340000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28518680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28520000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28521200000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28521560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28522880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28523685000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28524060000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28524780000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28525140000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28526000000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28530045000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28530480000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28531245000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28531680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28532355000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28532880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28533900000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28534080000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28534440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28535060000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28535520000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28536040000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28536200000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28536560000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28537200000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28538220000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28538580000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28538940000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28539675000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28540040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28540725000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28541055000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28541420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28541985000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28542180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28542540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28543160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28543697000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28543880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28544240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28544880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28545555000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28545740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28546100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28546740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28547295000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28547480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28547840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28548480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28549035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28549220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28549580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28550220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28550955000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28551140000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28551500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28552140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28552815000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28553145000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28553520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28554075000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28554260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28554620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28555125000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28555320000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28555680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28556300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28558125000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28558320000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28558680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28559300000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28560105000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28560300000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28560660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28561280000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28565175000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28565325000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28565475000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28565985000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28566165000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28566315000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28566945000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28567095000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28567725000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28568265000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28568565000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28569255000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28569405000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28570215000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28573125000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28573305000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28573635000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28573965000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28582665000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28600080000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28600800000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28605100000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28605920000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28606640000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28607760000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28609200000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28609740000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28616980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28617820000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28618660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28619865000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28623140000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28624060000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28625040000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28625880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28626480000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28662105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28662540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28663005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28663440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28664865000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28665555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28666095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28666695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28667265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28668900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28668900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28668900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28668900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28669620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28671060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28671060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28671060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28671060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28671780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28674820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28674820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28674820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28674820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28675540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28676355000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28677060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28677780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28679055000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28679760000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28681905000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28682340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28682805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28683240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28684665000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28685355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28685895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28686495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28687065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28688700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28688700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28688700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28688700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28689420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28690860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28690860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28690860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28690860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28691580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28694620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28694620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28694620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28694620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28695340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28696155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28696860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28697580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28698855000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28699560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28701705000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28702140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28702605000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28703040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28704465000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28705155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28705695000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28706295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28706865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28708500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28708500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28708500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28708500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28709220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28710660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28710660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28710660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28710660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28711380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28714420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28714420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28714420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28714420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28715140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28715955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28716660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28717380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28718655000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28719360000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28721340000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28721520000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28721880000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28723380000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28723560000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28723740000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28723920000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28724520000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28724720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28724920000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28725120000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28728345000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28728740000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28728820000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28729160000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28730595000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28732100000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28733060000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28733400000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28737920000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28738280000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28740000000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28740360000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28742280000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28742640000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28744875000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28745145000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28745540000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28745900000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28746260000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28746620000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28747755000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28748120000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28748840000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28749200000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28751565000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28751940000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28752660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28752740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28753740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28754720000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28755800000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28756160000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28756520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28757160000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28757980000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28758320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28759740000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28760940000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28761300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28762700000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28763505000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28763880000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28764600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28764960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28765820000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28770075000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28770500000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28771305000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28771740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28772445000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28772960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28774200000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28774380000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28774740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28775360000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28775820000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28776520000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28776680000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28777040000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28777680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28778880000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28779240000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28779600000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28780365000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28780740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28781415000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28781745000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28782120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28782675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28782860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28783220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28783860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28784417000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28784600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28784960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28785600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28786275000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28786460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28786820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28787460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28788015000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28788200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28788560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28789200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28789755000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28789940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28790300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28790940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28791705000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28791900000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28792260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28792880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28793565000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28793895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28794260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28794825000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28795020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28795380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28795905000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28796100000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28796460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28797080000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28798905000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28799100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28799460000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28800080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28800885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28801080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28801440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28802060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28805985000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28806165000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28806345000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28806885000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28807095000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28807275000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28807935000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28808115000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28808775000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28809345000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28809675000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28810395000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28810575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28811415000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28814355000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28814565000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28814925000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28815285000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28824015000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28842880000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28843780000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28848440000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28849260000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28849980000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28851100000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28852560000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28853280000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28860520000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28861360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28862200000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28863435000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28866800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28867720000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28868700000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28869540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28870140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28905795000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28906200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28906695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28907100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28908555000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28909245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28909905000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28910475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28911045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28912660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28912660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28912660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28912660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28913380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28914840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28914840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28914840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28914840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28915560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28918700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28918700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28918700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28918700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28919420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28920225000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28920940000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28921660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28922955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28923660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28925835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28926240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28926735000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28927140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28928595000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28929285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28929945000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28930515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28931085000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28932700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28932700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28932700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28932700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28933420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28934880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28934880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28934880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28934880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28935600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28938740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28938740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28938740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28938740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28939460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28940265000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28940980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28941700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28942995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28943700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28945875000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28946280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28946775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28947180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28948635000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28949325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28949985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28950555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28951125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28952740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28952740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28952740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28952740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28953460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28954920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28954920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28954920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28954920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28955640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28958780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28958780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28958780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28958780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28959500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28960305000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28961020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28961740000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28963035000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28963740000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28965720000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28965900000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28966260000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28967760000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28967940000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28968120000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28968300000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28968900000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28969100000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28969300000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28969500000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28972725000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28973120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28973200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28973540000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28974975000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28976480000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28977440000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28977780000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28982400000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28982760000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28984480000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28984820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28986760000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28987100000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28989405000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28989705000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28990220000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28990580000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28990940000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28991300000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28992465000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28992840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28993560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28993920000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28996305000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28996680000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28997400000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28997480000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28998480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 28999460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29000540000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29000900000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29001260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29001900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29002720000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29003060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29004480000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29005680000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29006040000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29007440000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29008245000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29008620000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29009340000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29009700000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29010560000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29014845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29015280000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29016105000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29016540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29017275000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29017800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29019000000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29019180000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29019540000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29020160000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29020620000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29021320000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29021480000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29021840000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29022480000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29023680000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29024040000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29024400000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29025195000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29025560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29026245000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29026575000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29026940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29027505000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29027700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29028060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29028680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29029277000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29029460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29029820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29030460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29031135000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29031320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29031680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29032320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29032875000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29033060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29033420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29034060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29034615000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29034800000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29035160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29035800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29036595000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29036780000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29037140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29037780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29038455000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29038785000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29039160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29039715000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29039900000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29040260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29040825000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29041020000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29041380000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29042000000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29043825000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29044020000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29044380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29045000000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29045805000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29046000000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29046360000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29046980000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29050935000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29051145000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29051355000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29051925000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29052165000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29052375000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29053065000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29053275000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29053965000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29054565000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29054925000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29055675000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29055885000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29056755000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29059725000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29059965000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29060355000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29060745000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29069505000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29088420000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29089320000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29093980000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29094800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29095520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29096640000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29098080000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29098800000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29106260000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29107200000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29108120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29109225000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29112800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29113620000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29114580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29115420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29116020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29118860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29119845000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29120220000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29121380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29122065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29122440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29123760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29125245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29125620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29136980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29150685000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29151060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29151800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29152160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29152600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29153520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29153880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29154240000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29154600000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29155040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29155515000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29155580000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29156640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29157000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29157440000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29159340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29159700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29160060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29160420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29160860000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29161335000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29161400000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29164200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29166750000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29168700000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29171250000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29173160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29173520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29173600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29174240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29174600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29174680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29175320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29175680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29175760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29176400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29176760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29176840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29178620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29178980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29179060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29179700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29180060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29180140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29180780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29181140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29181220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29181860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29182220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29182300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29184080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29185080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29185440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29185520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29186180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29187180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29187540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29187620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29188280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29189280000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29189640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29189720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29190380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29191380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29191740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29191820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29193620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29194620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29195235000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29195300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29195960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29196960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29197575000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29197640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29198300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29199300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29199915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29199980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29200640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29201640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29202255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29202320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29202765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29203095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29203425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29203755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29204085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29204415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29204745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29206820000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29207805000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29208180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29209340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29210025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29210400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29211720000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29213205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29213580000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29224940000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29238645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29239020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29239760000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29240120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29240560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29241480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29241840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29242200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29242560000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29243000000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29243475000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29243540000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29244600000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29244960000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29245400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29247300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29247660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29248020000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29248380000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29248820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29249295000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29249360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29252160000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29254710000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29256660000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29259210000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29261120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29261480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29261560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29262200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29262560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29262640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29263280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29263640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29263720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29264360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29264720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29264800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29266580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29266940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29267020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29267660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29268020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29268100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29268740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29269100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29269180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29269820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29270180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29270260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29272040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29273040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29273400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29273480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29274140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29275140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29275500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29275580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29276240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29277240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29277600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29277680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29278340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29279340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29279700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29279780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29281580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29282580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29283195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29283260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29283920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29284920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29285535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29285600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29286260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29287260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29287875000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29287940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29288600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29289600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29290215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29290280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29290725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29291055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29291385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29291715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29292045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29292375000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29292705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29294780000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29295765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29296140000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29297300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29297985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29298360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29299680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29301165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29301540000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29312900000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29326605000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29326980000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29327720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29328080000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29328520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29329440000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29329800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29330160000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29330520000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29330960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29331435000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29331500000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29332560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29332920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29333360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29335260000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29335620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29335980000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29336340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29336780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29337255000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29337320000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29340120000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29342670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29344620000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29347170000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29349080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29349440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29349520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29350160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29350520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29350600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29351240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29351600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29351680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29352320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29352680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29352760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29354540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29354900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29354980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29355620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29355980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29356060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29356700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29357060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29357140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29357780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29358140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29358220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29360000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29361000000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29361360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29361440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29362100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29363100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29363460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29363540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29364200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29365200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29365560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29365640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29366300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29367300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29367660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29367740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29369540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29370540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29371155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29371220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29371880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29372880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29373495000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29373560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29374220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29375220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29375835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29375900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29376560000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29377560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29378175000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29378240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29378685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29379015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29379345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29379675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29380005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29380335000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29380665000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29382740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29383725000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29384100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29385260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29385945000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29386320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29387640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29389125000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29389500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29400860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29414565000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29414940000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29415680000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29416040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29416480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29417400000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29417760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29418120000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29418480000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29418920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29419395000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29419460000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29420520000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29420880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29421320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29423220000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29423580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29423940000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29424300000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29424740000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29425215000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29425280000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29428080000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29430630000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29432580000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29435130000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29437040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29437400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29437480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29438120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29438480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29438560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29439200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29439560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29439640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29440280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29440640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29440720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29442500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29442860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29442940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29443580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29443940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29444020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29444660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29445020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29445100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29445740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29446100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29446180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29447960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29448960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29449320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29449400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29450060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29451060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29451420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29451500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29452160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29453160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29453520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29453600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29454260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29455260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29455620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29455700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29457500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29458500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29459115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29459180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29459840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29460840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29461455000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29461520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29462180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29463180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29463795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29463860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29464520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29465520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29466135000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29466200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29466645000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29466975000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29467305000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29467635000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29467965000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29468295000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29468625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29470935000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29471625000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29472000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29472495000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29473185000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29473560000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29474055000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29474745000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29475120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29475645000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29476365000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29476740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29477625000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29478345000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29478720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29479605000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29480325000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29480700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29482095000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29482785000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29483160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29484555000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29485245000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29485620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29486445000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29486820000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29488995000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29489685000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29490060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29503220000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29513240000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29534620000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29537540000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29538225000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29550320000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29560940000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29562045000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29563005000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29563455000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29563815000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29564175000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29564925000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29565585000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29566245000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29568165000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29568525000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29569275000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29569935000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29571435000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29571615000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29571825000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572215000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572425000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29572995000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29573175000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29573385000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29573595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29573805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29574435000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29574800000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29579175000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29582265000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29584060000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29588660000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29591340000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29627625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29628020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29628405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29628820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29630145000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29630805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29631315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29631885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29632485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29634040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29634040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29634040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29634040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29634640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29635980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29635980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29635980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29635980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29636580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29639260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29639260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29639260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29639260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29639860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29640675000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29641460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29642260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29643615000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29644400000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29646705000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29647100000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29647485000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29647900000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29649225000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29649885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29650395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29650965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29651565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29653120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29653120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29653120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29653120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29653720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29655060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29655060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29655060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29655060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29655660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29658340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29658340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29658340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29658340000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29658940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29659755000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29660540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29661340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29662695000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29663480000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29665785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29666180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29666565000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29666980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29668305000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29668965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29669475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29670045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29670645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29672200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29672200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29672200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29672200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29672800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29674140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29674140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29674140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29674140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29674740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29677420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29677420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29677420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29677420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29678020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29678835000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29679620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29680420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29681775000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29682560000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29684800000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29685000000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29685360000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29687040000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29687240000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29687420000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29687600000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29688260000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29688480000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29688680000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29688880000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29692185000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29692600000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29692680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29693060000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29694585000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29696080000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29697080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29697440000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29701660000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29702020000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29703500000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29703880000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29705680000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29706040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29708145000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29708355000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29708800000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29709160000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29709520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29709880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29711025000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29711420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29712160000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29712520000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29714775000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29715160000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29715880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29715960000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29717020000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29718040000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29719000000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29719360000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29719720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29720380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29721100000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29721460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29722740000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29723820000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29724200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29725500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29726325000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29726720000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29727460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29727820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29728760000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29732895000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29733340000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29734095000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29734540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29735205000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29735740000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29736880000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29737040000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29737420000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29738080000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29738540000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29739120000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29739300000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29739680000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29740360000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29741500000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29741860000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29742220000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29742975000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29743360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29744055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29744385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29744780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29745375000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29745560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29745940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29746600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29747117000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29747300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29747680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29748340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29749035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29749220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29749600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29750260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29750835000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29751020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29751400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29752060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29752635000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29752820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29753200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29753860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29754615000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29754800000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29755180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29755840000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29756535000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29756865000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29757260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29757855000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29758040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29758420000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29758905000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29759100000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29759480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29760160000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29762115000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29762300000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29762680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29763340000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29764245000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29764440000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29764820000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29765500000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29769465000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29769585000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29769705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29770215000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29770365000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29770485000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29771085000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29771205000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29771805000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29772375000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29772615000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29773275000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29773395000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29774145000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29778255000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29778405000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29778675000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29778945000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29785905000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29803480000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29804280000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29808420000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29809260000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29809860000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29810820000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29812180000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29812780000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29819500000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29820300000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29821120000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29822325000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29825200000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29826160000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29827140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29828020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29828620000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29864775000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29865140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29865555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29865940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29867295000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29867955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29868465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29869065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29869635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29871180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29871180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29871180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29871180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29871780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29873140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29873140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29873140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29873140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29873740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29876400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29876400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29876400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29876400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29877000000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29877825000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29878620000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29879420000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29880795000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29881580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29883915000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29884280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29884695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29885080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29886435000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29887095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29887605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29888205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29888775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29890320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29890320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29890320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29890320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29890920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29892280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29892280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29892280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29892280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29892880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29895540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29895540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29895540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29895540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29896140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29896965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29897760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29898560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29899935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29900720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29903055000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29903420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29903835000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29904220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29905575000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29906235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29906745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29907345000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29907915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29909460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29909460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29909460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29909460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29910060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29911420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29911420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29911420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29911420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29912020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29914680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29914680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29914680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29914680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29915280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29916105000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29916900000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29917700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29919075000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29919860000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29922100000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29922300000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29922660000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29924340000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29924540000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29924720000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29924900000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29925560000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29925780000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29925980000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29926180000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29929485000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29929900000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29929980000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29930360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29931885000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29933380000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29934380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29934740000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29938960000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29939320000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29940800000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29941180000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29942980000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29943340000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29945475000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29945715000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29946100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29946460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29946820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29947180000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29948355000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29948740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29949460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29949820000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29952135000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29952520000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29953240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29953320000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29954380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29955400000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29956360000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29956720000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29957080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29957740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29958460000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29958820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29960100000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29961180000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29961560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29962860000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29963685000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29964080000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29964820000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29965180000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29966120000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29970285000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29970740000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29971545000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29972000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29972715000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29973260000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29974420000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29974580000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29974960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29975620000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29976080000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29976660000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29976840000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29977220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29977900000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29979040000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29979400000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29979760000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29980545000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29980940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29981655000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29981985000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29982380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29982975000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29983160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29983540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29984200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29984747000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29984940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29985320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29986000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29986695000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29986880000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29987260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29987920000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29988495000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29988680000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29989060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29989720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29990295000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29990480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29990860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29991520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29992305000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29992500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29992880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29993560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29994255000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29994585000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29994980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29995575000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29995760000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29996140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29996655000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29996840000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29997220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29997880000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 29999835000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30000020000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30000400000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30001060000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30001965000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30002160000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30002540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30003220000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30007455000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30007605000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30007755000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30008265000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30008445000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30008595000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30009195000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30009345000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30009975000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30010545000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30010815000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30011505000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30011655000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30012435000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30016575000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30016755000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30017055000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30017355000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30024345000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30042000000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30042800000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30047140000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30047980000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30048580000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30049540000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30050880000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30051480000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30058240000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30059040000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30059860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30061095000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30063960000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30064800000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30065800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30066660000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30067260000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30103965000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30104500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30104955000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30105500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30106875000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30107565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30108195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30108795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30109365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30111000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30111000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30111000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30111000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30111600000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30113080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30113080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30113080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30113080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30113680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30116460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30116460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30116460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30116460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30117060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30117885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30118680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30119480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30120855000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30121640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30124005000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30124540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30124995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30125540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30126915000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30127605000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30128235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30128835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30129405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30131040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30131040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30131040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30131040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30131640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30133120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30133120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30133120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30133120000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30133720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30136500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30136500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30136500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30136500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30137100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30137925000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30138720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30139520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30140895000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30141680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30144045000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30144580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30145035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30145580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30146955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30147645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30148275000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30148875000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30149445000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30151080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30151080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30151080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30151080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30151680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30153160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30153160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30153160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30153160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30153760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30156540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30156540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30156540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30156540000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30157140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30157965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30158760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30159560000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30160935000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30161720000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30163960000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30164160000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30164520000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30166200000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30166400000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30166580000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30166760000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30167420000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30167640000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30167840000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30168040000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30171345000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30171760000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30171840000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30172220000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30173745000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30175240000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30176240000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30176600000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30180940000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30181300000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30182780000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30183160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30184960000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30185320000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30187485000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30187755000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30188280000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30188660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30189040000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30189400000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30190605000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30191000000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30191740000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30192100000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30194475000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30194860000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30195580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30195660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30196720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30197740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30198900000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30199280000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30199660000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30200320000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30201160000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30201520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30202920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30204120000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30204500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30205920000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30206745000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30207140000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30207880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30208240000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30209180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30213375000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30213820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30214635000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30215080000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30215805000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30216340000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30217480000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30217640000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30218020000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30218680000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30219140000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30219720000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30219900000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30220280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30220960000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30222100000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30222460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30222820000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30223635000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30224020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30224715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30225045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30225440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30226035000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30226220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30226600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30227260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30227837000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30228020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30228400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30229060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30229755000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30229940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30230320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30230980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30231555000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30231740000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30232120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30232780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30233355000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30233540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30233920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30234580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30235395000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30235580000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30235960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30236620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30237315000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30237645000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30238040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30238635000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30238820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30239200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30239745000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30239940000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30240320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30241000000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30242955000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30243140000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30243520000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30244180000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30245085000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30245280000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30245660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30246340000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30250605000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30250785000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30250965000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30251535000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30251745000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30251925000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30252585000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30252765000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30253425000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30254055000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30254355000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30255075000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30255255000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30256065000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30260235000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30260445000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30260775000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30261105000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30268125000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30285760000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30286560000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30291080000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30291920000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30292720000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30293800000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30295260000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30295860000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30302860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30303780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30304720000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30305985000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30308980000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30309940000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30310920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30311800000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30312400000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30349935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30350440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30350925000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30351440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30352845000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30353565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30354195000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30354765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30355365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30357780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30359260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30359260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30359260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30359260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30360060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30362860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30362860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30362860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30362860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30363660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30364485000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30365280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30366080000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30367455000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30368240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30370635000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30371140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30371625000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30372140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30373545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30374265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30374895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30375465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30376065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30377680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30377680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30377680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30377680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30378480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30379960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30379960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30379960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30379960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30380760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30383560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30383560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30383560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30383560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30384360000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30385185000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30385980000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30386780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30388155000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30388940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30391335000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30391840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30392325000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30392840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30394245000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30394965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30395595000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30396165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30396765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30398380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30398380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30398380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30398380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30399180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30400660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30400660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30400660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30400660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30401460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30404260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30404260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30404260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30404260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30405060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30405885000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30406680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30407480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30408855000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30409640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30411880000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30412080000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30412440000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30414120000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30414320000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30414500000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30414680000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30415340000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30415560000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30415760000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30415960000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30419475000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30419920000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30420000000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30420380000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30421905000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30423400000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30424400000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30424760000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30429540000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30429920000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30431820000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30432200000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30434240000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30434620000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30437055000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30437355000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30437820000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30438200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30438580000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30438940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30440175000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30440560000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30441280000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30441640000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30444075000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30444460000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30445180000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30445260000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30446320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30447340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30448500000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30448880000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30449260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30449920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30450760000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30451120000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30452520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30453720000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30454100000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30455520000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30456345000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30456740000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30457480000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30457840000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30458780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30463455000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30463900000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30464745000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30465200000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30465975000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30466520000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30467880000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30468060000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30468440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30469120000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30469580000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30470360000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30470540000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30470920000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30471580000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30472920000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30473300000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30473680000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30474525000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30474920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30475635000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30475965000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30476360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30476955000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30477140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30477520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30478180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30478787000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30478980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30479360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30480040000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30480735000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30480920000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30481300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30481960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30482535000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30482720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30483100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30483760000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30484335000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30484520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30484900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30485560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30486405000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30486600000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30486980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30487660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30488355000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30488685000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30489080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30489675000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30489860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30490240000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30490815000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30491000000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30491380000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30492040000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30493995000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30494180000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30494560000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30495220000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30496125000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30496320000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30496700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30497380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30501675000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30501885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30502095000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30502665000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30502905000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30503115000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30503775000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30503985000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30504675000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30505305000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30505635000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30506385000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30506595000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30507435000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30511635000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30511875000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30512235000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30512595000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30519645000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30537360000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30538360000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30542880000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30543720000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30544520000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30545600000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30547080000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30547880000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30554860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30555780000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30556720000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30557895000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30561120000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30561960000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30562960000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30563820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30564420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30567600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30568725000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30569120000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30570460000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30571335000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30571720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30573240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30574965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30575360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30588700000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30604665000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30605060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30605940000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30606320000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30606780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30607740000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30608120000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30608500000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30608860000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30609300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30609825000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30609900000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30611140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30611500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30611940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30614100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30614480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30614860000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30615220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30615660000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30616185000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30616260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30619520000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30622260000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30624560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30627300000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30629380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30629740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30629820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30630580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30630940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30631020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30631780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30632140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30632220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30632980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30633340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30633420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30635380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30635740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30635820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30636580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30636940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30637020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30637780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30638140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30638220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30638980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30639340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30639420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30641380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30642400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30642760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30642840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30643600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30644620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30644980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30645060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30645820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30646840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30647200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30647280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30648040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30649060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30649420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30649500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30651460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30652480000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30653115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30653180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30653920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30654940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30655575000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30655640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30656380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30657400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30658035000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30658100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30658840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30659860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30660495000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30660560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30661005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30661335000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30661665000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30661995000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30662325000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30662655000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30662985000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30665300000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30666435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30666820000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30668140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30669015000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30669400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30670920000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30672645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30673040000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30686380000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30702345000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30702740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30703620000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30704000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30704460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30705420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30705800000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30706180000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30706540000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30706980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30707505000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30707580000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30708820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30709180000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30709620000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30711780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30712160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30712540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30712900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30713340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30713865000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30713940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30717200000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30719940000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30722240000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30724980000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30727060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30727420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30727500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30728260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30728620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30728700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30729460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30729820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30729900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30730660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30731020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30731100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30733060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30733420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30733500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30734260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30734620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30734700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30735460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30735820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30735900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30736660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30737020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30737100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30739060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30740080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30740440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30740520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30741280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30742300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30742660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30742740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30743500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30744520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30744880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30744960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30745720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30746740000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30747100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30747180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30749140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30750160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30750795000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30750860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30751600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30752620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30753255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30753320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30754060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30755080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30755715000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30755780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30756520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30757540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30758175000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30758240000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30758685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30759015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30759345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30759675000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30760005000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30760335000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30760665000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30762980000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30764115000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30764500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30765820000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30766695000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30767080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30768600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30770325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30770720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30784060000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30800025000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30800420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30801300000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30801680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30802140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30803100000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30803480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30803860000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30804220000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30804660000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30805185000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30805260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30806500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30806860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30807300000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30809460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30809840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30810220000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30810580000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30811020000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30811545000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30811620000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30814880000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30817620000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30819920000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30822660000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30824740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30825100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30825180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30825940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30826300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30826380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30827140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30827500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30827580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30828340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30828700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30828780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30830740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30831100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30831180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30831940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30832300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30832380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30833140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30833500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30833580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30834340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30834700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30834780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30836740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30837760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30838120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30838200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30838960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30839980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30840340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30840420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30841180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30842200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30842560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30842640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30843400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30844420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30844780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30844860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30846820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30847840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30848475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30848540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30849280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30850300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30850935000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30851000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30851740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30852760000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30853395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30853460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30854200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30855220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30855855000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30855920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30856365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30856695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30857025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30857355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30857685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30858015000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30858345000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30860660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30861795000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30862180000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30863500000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30864375000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30864760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30866280000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30868005000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30868400000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30881740000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30897705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30898100000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30898980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30899360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30899820000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30900780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30901160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30901540000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30901900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30902340000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30902865000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30902940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30904180000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30904540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30904980000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30907140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30907520000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30907900000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30908260000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30908700000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30909225000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30909300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30912560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30915300000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30917600000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30920340000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30922420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30922780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30922860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30923620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30923980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30924060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30924820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30925180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30925260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30926020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30926380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30926460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30928420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30928780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30928860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30929620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30929980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30930060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30930820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30931180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30931260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30932020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30932380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30932460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30934420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30935440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30935800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30935880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30936640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30937660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30938020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30938100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30938860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30939880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30940240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30940320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30941080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30942100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30942460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30942540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30944500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30945520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30946155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30946220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30946960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30947980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30948615000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30948680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30949420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30950440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30951075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30951140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30951880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30952900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30953535000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30953600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30954045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30954375000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30954705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30955035000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30955365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30955695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30956025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30958575000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30959295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30959680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30960225000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30960975000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30961360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30961905000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30962655000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30963040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30963705000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30964455000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30964840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30965895000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30966615000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30967000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30968055000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30968775000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30969160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30970815000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30971535000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30971920000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30973575000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30974295000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30974680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30975675000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30976060000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30978495000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30979215000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30979600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 30994940000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31006840000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31032220000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31035480000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31036215000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31050340000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31062820000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31064055000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31065165000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31065600000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31065915000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31066245000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31067025000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31067715000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31068405000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31070460000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31070775000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31071555000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31072245000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31073895000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31074075000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31074285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31074495000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31074675000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31074885000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31075095000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31075275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31075455000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31075635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31075845000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31076055000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31076265000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31076955000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31077340000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31082025000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31085385000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31087320000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31091900000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31094760000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31132365000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31132840000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31133235000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31133720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31134975000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31135665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31136235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31136775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31137315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31138900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31138900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31138900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31138900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31139560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31140980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31140980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31140980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31140980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31141640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31144020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31144020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31144020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31144020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31144680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31145535000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31146180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31146840000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31148295000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31148940000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31151445000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31151920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31152315000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31152800000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31154055000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31154745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31155315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31155855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31156395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31157980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31157980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31157980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31157980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31158640000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31160060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31160060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31160060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31160060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31160720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31163100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31163100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31163100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31163100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31163760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31164615000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31165260000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31165920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31167375000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31168020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31170525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31171000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31171395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31171880000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31173135000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31173825000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31174395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31174935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31175475000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31177060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31177060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31177060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31177060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31177720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31179140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31179140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31179140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31179140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31179800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31182180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31182180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31182180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31182180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31182840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31183695000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31184340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31185000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31186455000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31187100000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31189560000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31189780000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31190140000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31191980000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31192200000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31192380000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31192560000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31193280000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31193520000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31193720000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31193920000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31197525000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31197960000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31198040000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31198440000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31200105000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31201720000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31202800000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31203180000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31207400000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31207800000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31209420000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31209820000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31211680000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31212060000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31214355000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31214565000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31215100000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31215480000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31215880000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31216260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31217505000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31217920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31218700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31219080000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31221405000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31221820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31222600000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31222680000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31223800000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31224900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31225960000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31226340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31226740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31227460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31228280000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31228680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31230020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31231140000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31231540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31232880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31233735000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31234140000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31234920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31235320000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31236340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31240845000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31241320000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31242105000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31242580000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31243275000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31243840000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31245100000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31245260000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31245660000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31246380000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31246880000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31247520000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31247700000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31248100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31248820000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31250080000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31250460000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31250860000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31251675000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31252080000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31252815000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31253145000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31253560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31254165000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31254360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31254760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31255480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31256027000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31256220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31256620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31257340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31258065000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31258260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31258660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31259380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31259985000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31260180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31260580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31261300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31261905000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31262100000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31262500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31263220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31264035000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31264220000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31264620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31265340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31266075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31266405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31266820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31267425000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31267620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31268020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31268535000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31268720000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31269120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31269840000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31271985000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31272180000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31272580000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31273300000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31274145000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31274340000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31274740000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31275460000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31279815000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31279935000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31280055000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31280565000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31280715000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31280835000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31281405000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31281525000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31282095000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31282695000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31282905000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31283595000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31283715000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31284465000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31289835000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31289985000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31290225000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31290465000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31295715000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31312340000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31313220000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31317260000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31318120000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31318780000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31319740000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31321160000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31321820000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31328040000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31328940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31329840000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31331145000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31333680000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31334500000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31335520000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31336420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31337020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31374525000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31374980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31375395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31375860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31377165000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31377855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31378425000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31378965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31379505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31381100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31381100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31381100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31381100000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31381760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31383160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31383160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31383160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31383160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31383820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31386220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31386220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31386220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31386220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31386880000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31387725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31388380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31389040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31390485000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31391140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31393665000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31394120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31394535000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31395000000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31396305000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31396995000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31397565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31398105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31398645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31400240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31400240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31400240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31400240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31400900000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31402300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31402300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31402300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31402300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31402960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31405360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31405360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31405360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31405360000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31406020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31406865000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31407520000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31408180000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31409625000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31410280000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31412805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31413260000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31413675000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31414140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31415445000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31416135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31416705000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31417245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31417785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31419380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31419380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31419380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31419380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31420040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31421440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31421440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31421440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31421440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31422100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31424500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31424500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31424500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31424500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31425160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31426005000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31426660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31427320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31428765000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31429420000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31431880000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31432100000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31432460000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31434280000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31434500000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31434680000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31434860000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31435580000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31435820000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31436020000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31436220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31439835000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31440300000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31440380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31440780000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31442445000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31444060000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31445140000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31445520000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31449740000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31450140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31451760000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31452160000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31454020000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31454400000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31456725000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31456965000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31457440000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31457820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31458220000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31458600000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31459875000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31460280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31461060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31461460000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31463835000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31464240000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31465020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31465100000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31466220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31467360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31468420000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31468800000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31469200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31469920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31470740000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31471140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31472480000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31473600000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31474000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31475340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31476195000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31476600000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31477380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31477780000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31478800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31483335000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31483800000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31484625000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31485100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31485825000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31486380000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31487640000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31487820000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31488220000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31488940000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31489440000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31490080000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31490240000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31490640000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31491360000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31492620000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31493020000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31493400000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31494255000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31494660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31495395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31495725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31496140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31496745000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31496940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31497340000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31498060000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31498637000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31498820000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31499220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31499940000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31500675000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31500860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31501260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31501980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31502595000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31502780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31503180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31503900000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31504515000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31504700000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31505100000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31505820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31506675000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31506860000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31507260000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31507980000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31508715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31509045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31509460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31510065000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31510260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31510660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31511205000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31511400000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31511800000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31512520000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31514655000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31514840000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31515240000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31515960000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31516845000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31517040000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31517440000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31518160000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31522545000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31522695000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31522845000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31523385000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31523565000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31523715000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31524315000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31524465000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31525065000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31525695000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31525935000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31526655000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31526805000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31527585000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31532985000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31533165000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31533435000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31533705000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31538985000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31555600000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31556480000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31560740000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31561600000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31562260000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31563220000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31564640000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31565300000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31571520000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31572420000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31573320000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31574655000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31577180000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31578000000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31579020000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31579920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31580520000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31618065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31618480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31618935000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31619360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31620675000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31621395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31621965000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31622505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31623045000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31624600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31624600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31624600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31624600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31625260000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31626680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31626680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31626680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31626680000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31627340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31629720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31629720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31629720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31629720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31630380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31631235000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31631880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31632540000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31633995000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31634640000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31637205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31637620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31638075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31638500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31639815000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31640535000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31641105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31641645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31642185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31643740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31643740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31643740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31643740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31644400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31645820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31645820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31645820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31645820000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31646480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31648860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31648860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31648860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31648860000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31649520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31650375000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31651020000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31651680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31653135000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31653780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31656345000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31656760000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31657215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31657640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31658955000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31659675000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31660245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31660785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31661325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31662880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31662880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31662880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31662880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31663540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31664960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31664960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31664960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31664960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31665620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31668000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31668000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31668000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31668000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31668660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31669515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31670160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31670820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31672275000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31672920000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31675380000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31675600000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31675960000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31677800000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31678020000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31678200000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31678380000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31679100000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31679340000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31679540000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31679740000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31683345000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31683780000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31683860000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31684260000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31685925000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31687540000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31688620000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31689000000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31693220000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31693620000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31695240000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31695640000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31697500000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31697880000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31700235000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31700505000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31700920000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31701300000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31701700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31702080000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31703385000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31703800000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31704580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31704960000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31707375000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31707780000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31708560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31708640000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31709760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31710900000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31711960000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31712340000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31712740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31713460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31714280000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31714680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31716020000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31717140000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31717540000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31718880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31719735000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31720140000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31720920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31721320000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31722340000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31726905000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31727380000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31728225000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31728700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31729455000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31730020000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31731280000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31731440000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31731840000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31732560000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31733060000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31733700000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31733880000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31734280000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31735000000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31736260000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31736640000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31737040000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31737915000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31738320000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31739055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31739385000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31739800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31740405000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31740600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31741000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31741720000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31742327000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31742520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31742920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31743640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31744365000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31744560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31744960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31745680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31746285000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31746480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31746880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31747600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31748205000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31748400000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31748800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31749520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31750395000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31750580000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31750980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31751700000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31752435000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31752765000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31753180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31753785000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31753980000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31754380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31754955000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31755140000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31755540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31756260000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31758405000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31758600000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31759000000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31759720000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31760565000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31760760000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31761160000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31761880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31766535000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31766715000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31766895000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31767465000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31767675000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31767855000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31768485000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31768665000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31769295000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31769955000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31770225000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31770975000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31771155000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31771965000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31777395000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31777605000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31777905000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31778205000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31783515000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31800260000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31801140000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31805580000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31806440000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31807100000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31808060000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31809460000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31810120000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31816560000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31817460000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31818360000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31819725000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31822400000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31823360000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31824360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31825260000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31825860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31863435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31864040000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31864515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31865140000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31866495000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31867245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31867815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31868505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31869165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31870840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31870840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31870840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31870840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31871500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31872920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31872920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31872920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31872920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31873580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31875960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31875960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31875960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31875960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31876620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31877475000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31878120000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31878780000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31880235000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31880880000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31883475000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31884080000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31884555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31885180000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31886535000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31887285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31887855000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31888545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31889205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31890880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31890880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31890880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31890880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31891540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31892960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31892960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31892960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31892960000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31893620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31896000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31896000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31896000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31896000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31896660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31897515000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31898160000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31898820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31900275000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31900920000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31903515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31904120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31904595000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31905220000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31906575000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31907325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31907895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31908585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31909245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31910920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31910920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31910920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31910920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31911580000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31913000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31913000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31913000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31913000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31913660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31916040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31916040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31916040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31916040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31916700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31917555000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31918200000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31918860000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31920315000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31920960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31923420000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31923640000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31924000000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31925840000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31926060000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31926240000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31926420000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31927140000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31927380000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31927580000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31927780000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31931385000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31931820000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31931900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31932300000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31933965000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31935580000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31936660000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31937040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31941400000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31941780000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31943400000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31943800000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31945660000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31946040000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31948425000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31948725000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31949300000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31949700000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31950100000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31950480000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31951815000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31952220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31953000000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31953400000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31955865000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31956280000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31957060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31957140000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31958260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31959360000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31960420000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31960800000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31961200000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31961920000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31962740000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31963140000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31964480000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31965600000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31966000000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31967340000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31968195000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31968600000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31969380000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31969780000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31970800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31975395000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31975860000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31976745000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31977220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31978005000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31978560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31979820000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31980000000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31980400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31981120000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31981620000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31982260000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31982420000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31982820000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31983540000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31984800000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31985200000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31985580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31986495000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31986900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31987635000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31987965000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31988380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31988985000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31989180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31989580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31990300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31990937000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31991120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31991520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31992240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31992975000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31993160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31993560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31994280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31994895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31995080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31995480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31996200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31996815000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31997000000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31997400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31998120000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31999035000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31999220000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 31999620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32000340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32001075000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32001405000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32001820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32002425000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32002620000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32003020000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32003625000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32003820000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32004220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32004940000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32007075000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32007260000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32007660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32008380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32009265000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32009460000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32009860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32010580000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32015265000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32015475000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32015685000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32016285000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32016525000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32016735000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32017395000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32017605000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32018265000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32018955000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32019255000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32020035000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32020245000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32021085000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32026545000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32026785000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32027115000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32027445000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32032785000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32051620000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32052500000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32056940000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32057800000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32058460000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32059420000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32060840000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32061500000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32067900000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32068800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32069700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32071005000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32073820000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32074640000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32075640000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32076540000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32077140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32080520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32081325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32081740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32083000000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32083605000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32084020000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32085400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32086515000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32086920000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32094800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32105385000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32105800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32106660000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32107060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32107520000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32108460000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32108860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32109240000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32109640000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32110100000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32110695000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32110760000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32111820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32112220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32112680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32114280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32114680000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32115060000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32115460000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32115920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32116515000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32116580000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32119700000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32122260000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32124300000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32126850000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32128980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32129380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32129460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32130180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32130580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32130660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32131380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32131780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32131860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32132580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32132980000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32133060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32135100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32135500000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32135580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32136300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32136700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32136780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32137500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32137900000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32137980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32138700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32139100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32139180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32141220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32142340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32142720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32142800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32143500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32144620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32145000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32145080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32145780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32146900000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32147280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32147360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32148060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32149180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32149560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32149640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32151660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32152780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32153475000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32153540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32154240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32155360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32156055000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32156120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32156820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32157940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32158635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32158700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32159400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32160520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32161215000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32161280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32161725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32162055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32162385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32162715000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32163045000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32163375000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32163705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32166180000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32166975000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32167380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32168660000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32169285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32169700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32171080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32172195000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32172600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32180480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32191065000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32191480000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32192340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32192740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32193200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32194140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32194540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32194920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32195320000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32195780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32196375000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32196440000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32197500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32197900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32198360000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32199960000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32200360000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32200740000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32201140000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32201600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32202195000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32202260000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32205380000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32207940000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32209980000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32212530000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32214660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32215060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32215140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32215860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32216260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32216340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32217060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32217460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32217540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32218260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32218660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32218740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32220780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32221180000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32221260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32221980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32222380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32222460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32223180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32223580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32223660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32224380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32224780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32224860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32226900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32228020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32228400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32228480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32229180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32230300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32230680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32230760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32231460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32232580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32232960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32233040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32233740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32234860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32235240000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32235320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32237340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32238460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32239155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32239220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32239920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32241040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32241735000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32241800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32242500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32243620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32244315000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32244380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32245080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32246200000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32246895000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32246960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32247405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32247735000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32248065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32248395000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32248725000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32249055000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32249385000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32251860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32252655000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32253060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32254340000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32254965000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32255380000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32256760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32257875000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32258280000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32266160000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32276745000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32277160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32278020000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32278420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32278880000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32279820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32280220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32280600000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32281000000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32281460000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32282055000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32282120000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32283180000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32283580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32284040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32285640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32286040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32286420000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32286820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32287280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32287875000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32287940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32291060000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32293620000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32295660000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32298210000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32300340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32300740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32300820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32301540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32301940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32302020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32302740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32303140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32303220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32303940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32304340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32304420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32306460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32306860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32306940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32307660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32308060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32308140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32308860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32309260000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32309340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32310060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32310460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32310540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32312580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32313700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32314080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32314160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32314860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32315980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32316360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32316440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32317140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32318260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32318640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32318720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32319420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32320540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32320920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32321000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32323020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32324140000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32324835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32324900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32325600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32326720000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32327415000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32327480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32328180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32329300000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32329995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32330060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32330760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32331880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32332575000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32332640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32333085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32333415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32333745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32334075000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32334405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32334735000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32335065000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32337540000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32338335000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32338740000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32340020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32340645000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32341060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32342440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32343555000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32343960000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32351840000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32362425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32362840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32363700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32364100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32364560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32365500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32365900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32366280000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32366680000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32367140000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32367735000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32367800000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32368860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32369260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32369720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32371320000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32371720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32372100000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32372500000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32372960000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32373555000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32373620000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32376740000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32379300000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32381340000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32383890000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32386020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32386420000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32386500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32387220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32387620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32387700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32388420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32388820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32388900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32389620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32390020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32390100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32392140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32392540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32392620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32393340000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32393740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32393820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32394540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32394940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32395020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32395740000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32396140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32396220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32398260000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32399380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32399760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32399840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32400540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32401660000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32402040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32402120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32402820000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32403940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32404320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32404400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32405100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32406220000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32406600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32406680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32408700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32409820000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32410515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32410580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32411280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32412400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32413095000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32413160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32413860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32414980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32415675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32415740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32416440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32417560000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32418255000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32418320000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32418765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32419095000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32419425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32419755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32420085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32420415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32420745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32423445000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32424255000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32424660000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32425155000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32425935000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32426340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32426835000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32427615000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32428020000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32428545000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32429355000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32429760000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32430525000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32431335000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32431740000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32432505000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32433315000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32433720000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32434815000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32435595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32436000000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32437095000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32437875000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32438280000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32438985000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32439400000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32441985000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32442795000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32443200000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32453260000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32459840000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32473900000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32477340000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32478015000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32486780000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32493740000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32494665000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32495445000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32495835000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32496135000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32496435000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32497125000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32497725000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32498325000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32500515000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32500815000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32501505000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32502105000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32503905000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32504085000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32504295000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32504505000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32504685000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32504895000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32505105000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32505285000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32505465000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32505645000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32505855000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32506065000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32506275000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32506995000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32507400000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32512455000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32515305000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32516820000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32521400000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32524080000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32562885000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32563440000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32563845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32564400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32565615000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32566305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32566935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32567565000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32568165000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32569840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32569840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32569840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32569840000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32570560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32572000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32572000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32572000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32572000000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32572720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32574800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32574800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32574800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32574800000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32575520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32576385000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32577100000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32577820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32579295000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32580000000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32582505000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32583060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32583465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32584020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32585235000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32585925000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32586555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32587185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32587785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32589460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32589460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32589460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32589460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32590180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32591620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32591620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32591620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32591620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32592340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32594420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32594420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32594420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32594420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32595140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32596005000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32596720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32597440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32598915000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32599620000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32602125000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32602680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32603085000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32603640000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32604855000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32605545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32606175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32606805000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32607405000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32609080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32609080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32609080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32609080000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32609800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32611240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32611240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32611240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32611240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32611960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32614040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32614040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32614040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32614040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32614760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32615625000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32616340000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32617060000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32618535000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32619240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32621760000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32622000000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32622360000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32624340000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32624580000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32624760000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32624940000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32625720000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32625980000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32626180000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32626380000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32630055000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32630540000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32630620000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32631020000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32632755000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32634500000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32635640000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32636040000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32640380000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32640800000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32642560000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32642960000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32644980000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32645400000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32647815000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32648025000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32648660000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32649080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32649500000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32649920000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32651235000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32651660000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32652500000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32652920000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32655315000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32655740000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32656580000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32656660000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32657820000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32658980000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32660120000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32660540000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32660960000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32661720000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32662480000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32662880000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32664220000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32665340000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32665760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32667100000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32667975000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32668400000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32669240000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32669660000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32670740000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32675445000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32675940000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32676735000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32677220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32677935000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32678520000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32679840000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32680020000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32680440000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32681180000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32681700000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32682400000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32682560000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32682980000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32683740000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32685060000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32685480000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32685900000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32686725000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32687160000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32687895000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32688225000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32688660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32689275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32689460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32689880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32690640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32691197000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32691380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32691800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32692560000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32693295000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32693480000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32693900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32694660000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32695275000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32695460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32695880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32696640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32697255000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32697440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32697860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32698620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32699445000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32699640000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32700060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32700800000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32701545000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32701875000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32702300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32702925000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32703120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32703540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32704065000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32704260000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32704680000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32705420000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32707605000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32707800000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32708220000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32708960000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32709885000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32710080000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32710500000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32711240000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32715765000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32715885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32716005000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32716545000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32716695000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32716815000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32717385000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32717505000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32718075000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32718705000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32718885000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32719575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32719695000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32720415000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32727015000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32727165000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32727375000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32727585000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32731125000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32748060000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32749020000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32753080000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32753780000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32754500000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32755420000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32756860000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32757580000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32763480000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32764440000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32765400000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32766795000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32768900000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32769820000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32770860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32771760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32772360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32811075000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32811600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32812035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32812560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32813805000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32814525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32815155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32815785000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32816385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32818060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32818060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32818060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32818060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32818780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32820220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32820220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32820220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32820220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32820940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32823020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32823020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32823020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32823020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32823740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32824605000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32825320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32826040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32827515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32828220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32830755000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32831280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32831715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32832240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32833485000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32834205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32834835000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32835465000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32836065000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32837740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32837740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32837740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32837740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32838460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32839900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32839900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32839900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32839900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32840620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32842700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32842700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32842700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32842700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32843420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32844285000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32845000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32845720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32847195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32847900000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32850435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32850960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32851395000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32851920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32853165000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32853885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32854515000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32855145000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32855745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32857420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32857420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32857420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32857420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32858140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32859580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32859580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32859580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32859580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32860300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32862380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32862380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32862380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32862380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32863100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32863965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32864680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32865400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32866875000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32867580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32870100000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32870340000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32870700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32872680000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32872920000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32873100000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32873280000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32874060000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32874320000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32874520000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32874720000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32878395000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32878880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32878960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32879360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32881095000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32882840000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32883980000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32884380000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32888720000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32889140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32890900000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32891300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32893320000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32893740000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32896185000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32896425000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32897000000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32897420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32897840000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32898260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32899605000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32900040000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32900880000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32901300000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32903685000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32904120000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32904960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32905040000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32906220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32907380000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32908520000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32908940000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32909360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32910120000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32910880000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32911280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32912620000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32913740000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32914160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32915500000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32916375000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32916800000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32917640000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32918060000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32919140000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32923875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32924360000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32925195000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32925680000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32926425000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32927000000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32928360000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32928540000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32928960000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32929700000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32930220000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32930920000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32931080000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32931500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32932260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32933580000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32934000000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32934420000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32935275000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32935700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32936445000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32936775000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32937200000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32937825000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32938020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32938440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32939180000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32939777000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32939960000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32940380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32941140000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32941875000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32942060000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32942480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32943240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32943855000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32944040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32944460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32945220000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32945835000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32946020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32946440000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32947200000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32948055000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32948240000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32948660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32949420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32950155000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32950485000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32950920000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32951535000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32951720000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32952140000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32952705000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32952900000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32953320000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32954060000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32956245000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32956440000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32956860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32957600000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32958525000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32958720000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32959140000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32959880000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32964435000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32964585000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32964735000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32965305000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32965485000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32965635000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32966235000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32966385000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32966985000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32967645000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32967855000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32968575000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32968725000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32969475000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32976105000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32976285000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32976525000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32976765000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32980335000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32997280000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 32998240000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33002300000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33003000000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33003720000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33004640000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33006080000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33006800000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33012660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33013620000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33014580000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33015945000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33018060000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33018820000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33019860000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33020760000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33021360000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33060105000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33060600000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33061065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33061560000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33062835000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33063555000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33064185000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33064815000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33065415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33067060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33067060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33067060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33067060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33067780000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33069220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33069220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33069220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33069220000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33069940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33072020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33072020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33072020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33072020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33072740000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33073605000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33074320000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33075040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33076515000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33077220000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33079785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33080280000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33080745000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33081240000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33082515000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33083235000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33083865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33084495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33085095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33086740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33086740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33086740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33086740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33087460000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33088900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33088900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33088900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33088900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33089620000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33091700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33091700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33091700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33091700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33092420000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33093285000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33094000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33094720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33096195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33096900000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33099465000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33099960000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33100425000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33100920000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33102195000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33102915000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33103545000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33104175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33104775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33106420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33106420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33106420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33106420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33107140000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33108580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33108580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33108580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33108580000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33109300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33111380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33111380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33111380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33111380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33112100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33112965000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33113680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33114400000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33115875000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33116580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33119100000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33119340000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33119700000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33121680000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33121920000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33122100000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33122280000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33123060000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33123320000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33123520000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33123720000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33127395000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33127880000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33127960000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33128360000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33130095000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33131840000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33132980000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33133380000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33137720000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33138140000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33139900000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33140300000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33142320000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33142740000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33145215000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33145485000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33146000000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33146420000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33146840000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33147260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33148635000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33149060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33149900000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33150320000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33152775000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33153200000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33154040000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33154120000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33155280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33156440000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33157580000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33158000000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33158420000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33159180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33159940000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33160340000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33161680000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33162800000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33163220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33164560000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33165435000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33165860000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33166700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33167120000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33168200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33172965000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33173460000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33174315000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33174800000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33175575000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33176160000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33177480000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33177660000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33178080000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33178820000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33179340000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33180040000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33180200000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33180620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33181380000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33182700000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33183120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33183540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33184425000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33184860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33185595000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33185925000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33186360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33186975000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33187160000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33187580000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33188340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33188957000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33189140000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33189560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33190320000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33191055000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33191240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33191660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33192420000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33193035000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33193220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33193640000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33194400000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33195015000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33195200000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33195620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33196380000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33197265000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33197460000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33197880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33198620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33199365000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33199695000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33200120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33200745000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33200940000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33201360000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33201945000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33202140000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33202560000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33203300000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33205485000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33205680000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33206100000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33206840000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33207765000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33207960000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33208380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33209120000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33213705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33213885000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33214065000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33214665000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33214875000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33215055000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33215685000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33215865000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33216495000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33217185000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33217425000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33218175000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33218355000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33219135000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33225795000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33226005000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33226275000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33226545000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33230145000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33247100000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33248060000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33252300000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33253000000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33253720000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33254640000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33256060000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33256780000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33262680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33263640000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33264600000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33265995000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33268260000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33269180000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33270220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33271140000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33271740000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33310515000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33310980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33311475000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33311940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33313245000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33314025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33314655000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33315285000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33315885000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33317500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33317500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33317500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33317500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33318220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33319660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33319660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33319660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33319660000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33320380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33322460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33322460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33322460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33322460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33323180000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33324045000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33324760000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33325480000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33326955000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33327660000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33330255000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33330720000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33331215000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33331680000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33332985000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33333765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33334395000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33335025000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33335625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33337240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33337240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33337240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33337240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33337960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33339400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33339400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33339400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33339400000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33340120000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33342200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33342200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33342200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33342200000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33342920000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33343785000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33344500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33345220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33346695000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33347400000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33349995000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33350460000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33350955000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33351420000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33352725000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33353505000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33354135000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33354765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33355365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33356980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33357700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33359140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33359140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33359140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33359140000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33359860000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33361940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33361940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33361940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33361940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33362660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33363525000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33364240000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33364960000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33366435000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33367140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33369660000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33369900000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33370260000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33372240000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33372480000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33372660000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33372840000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33373620000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33373880000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33374080000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33374280000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33377955000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33378440000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33378520000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33378920000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33380655000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33382400000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33383540000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33383940000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33388440000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33388860000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33390620000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33391040000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33393060000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33393480000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33395985000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33396285000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33396980000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33397400000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33397820000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33398240000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33399645000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33400080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33400920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33401340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33403785000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33404220000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33405060000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33405140000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33406320000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33407480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33408620000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33409040000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33409460000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33410220000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33410980000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33411380000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33412720000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33413840000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33414260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33415600000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33416475000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33416900000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33417740000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33418160000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33419240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33424035000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33424520000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33425415000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33425900000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33426705000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33427280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33428640000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33428820000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33429240000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33429980000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33430500000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33431200000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33431360000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33431780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33432540000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33433860000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33434280000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33434700000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33435615000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33436040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33436785000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33437115000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33437540000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33438165000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33438360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33438780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33439520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33440177000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33440360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33440780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33441540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33442275000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33442460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33442880000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33443640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33444255000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33444440000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33444860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33445620000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33446235000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33446420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33446840000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33447600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33448515000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33448700000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33449120000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33449880000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33450615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33450945000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33451380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33451995000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33452180000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33452600000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33453225000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33453420000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33453840000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33454580000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33456765000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33456960000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33457380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33458120000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33459045000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33459240000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33459660000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33460400000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33465015000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33465225000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33465435000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33466065000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33466305000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33466515000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33467175000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33467385000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33468045000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33468765000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33469035000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33469815000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33470025000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33470835000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33477525000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33477765000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33478065000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33478365000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33481995000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33498960000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33499920000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33504160000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33505040000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33505760000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33506680000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33508120000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33508840000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33514740000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33515700000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33516660000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33518025000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33520460000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33521380000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33522420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33523320000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33523920000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33527480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33528435000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33528860000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33530260000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33531075000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33531500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33533040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33534405000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33534840000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33544600000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33557445000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33557880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33558800000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33559220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33559720000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33560720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33561140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33561560000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33561980000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33562480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33563115000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33563180000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33564360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33564780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33565280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33567080000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33567500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33567920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33568340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33568840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33569475000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33569540000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33573000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33575730000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33578100000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33580830000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33583100000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33583520000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33583600000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33584360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33584780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33584860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33585620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33586040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33586120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33586880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33587300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33587380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33589520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33589940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33590020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33590780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33591200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33591280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33592040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33592460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33592540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33593300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33593720000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33593800000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33595940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33597120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33597540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33597620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33598400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33599580000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33600000000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33600080000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33600860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33602040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33602460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33602540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33603320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33604500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33604920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33605000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33607160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33608340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33609075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33609140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33609920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33611100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33611835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33611900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33612680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33613860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33614595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33614660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33615440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33616620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33617355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33617420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33617865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33618195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33618525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33618855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33619185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33619515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33619845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33622400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33623355000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33623780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33625180000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33625995000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33626420000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33627960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33629325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33629760000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33639520000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33652365000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33652800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33653720000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33654140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33654640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33655640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33656060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33656480000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33656900000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33657400000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33658035000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33658100000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33659280000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33659700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33660200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33662000000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33662420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33662840000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33663260000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33663760000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33664395000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33664460000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33667920000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33670650000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33673020000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33675750000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33678020000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33678440000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33678520000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33679280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33679700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33679780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33680540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33680960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33681040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33681800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33682220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33682300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33684440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33684860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33684940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33685700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33686120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33686200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33686960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33687380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33687460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33688220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33688640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33688720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33690860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33692040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33692460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33692540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33693320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33694500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33694920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33695000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33695780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33696960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33697380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33697460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33698240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33699420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33699840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33699920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33702080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33703260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33703995000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33704060000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33704840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33706020000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33706755000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33706820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33707600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33708780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33709515000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33709580000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33710360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33711540000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33712275000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33712340000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33712785000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33713115000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33713445000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33713775000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33714105000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33714435000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33714765000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33717320000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33718275000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33718700000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33720100000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33720915000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33721340000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33722880000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33724245000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33724680000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33734440000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33747285000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33747720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33748640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33749060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33749560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33750560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33750980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33751400000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33751820000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33752320000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33752955000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33753020000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33754200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33754620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33755120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33756920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33757340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33757760000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33758180000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33758680000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33759315000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33759380000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33762840000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33765570000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33767940000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33770670000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33772940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33773360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33773440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33774200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33774620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33774700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33775460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33775880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33775960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33776720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33777140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33777220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33779360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33779780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33779860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33780620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33781040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33781120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33781880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33782300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33782380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33783140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33783560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33783640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33785780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33786960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33787380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33787460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33788240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33789420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33789840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33789920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33790700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33791880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33792300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33792380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33793160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33794340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33794760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33794840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33797000000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33798180000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33798915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33798980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33799760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33800940000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33801675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33801740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33802520000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33803700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33804435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33804500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33805280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33806460000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33807195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33807260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33807705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33808035000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33808365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33808695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33809025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33809355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33809685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33812240000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33813195000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33813620000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33815020000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33815835000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33816260000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33817800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33819165000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33819600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33829360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33842205000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33842640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33843560000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33843980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33844480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33845480000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33845900000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33846320000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33846740000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33847240000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33847875000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33847940000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33849120000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33849540000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33850040000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33851840000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33852260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33852680000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33853100000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33853600000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33854235000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33854300000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33857760000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33860490000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33862860000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33865590000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33867860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33868280000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33868360000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33869120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33869540000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33869620000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33870380000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33870800000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33870880000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33871640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33872060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33872140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33874280000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33874700000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33874780000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33875540000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33875960000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33876040000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33876800000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33877220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33877300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33878060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33878480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33878560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33880700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33881880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33882300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33882380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33883160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33884340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33884760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33884840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33885620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33886800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33887220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33887300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33888080000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33889260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33889680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33889760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33891920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33893100000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33893835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33893900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33894680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33895860000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33896595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33896660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33897440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33898620000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33899355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33899420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33900200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33901380000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33902115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33902180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33902625000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33902955000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33903285000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33903615000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33903945000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33904275000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33904605000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33907395000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33908205000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33908640000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33909195000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33910005000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33910440000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33910995000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33911805000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33912240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33912885000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33913725000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33914160000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33915105000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33915945000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33916380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33917325000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33918165000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33918600000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33919965000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33920805000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33921240000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33922605000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33923445000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33923880000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33924765000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33925200000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33927855000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33928665000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33929100000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33940900000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33949360000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33967420000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33970820000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33971565000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33982240000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33991060000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33992115000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33993045000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33993480000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33993780000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33994080000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33994785000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33995415000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33996045000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33998300000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33998600000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33999315000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 33999945000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34001775000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34001955000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34002165000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34002375000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34002555000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34002765000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34002975000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34003155000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34003335000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34003515000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34003725000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34003935000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34004145000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34004895000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34005320000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34010415000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34013505000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34015120000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34019720000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34022580000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34063185000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34063820000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34064205000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34064860000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34066035000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34066755000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34067295000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34067985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34068495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34070040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34070040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34070040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34070040000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34070820000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34072240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34072240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34072240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34072240000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34073020000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34074780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34074780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34074780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34074780000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34075560000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34076445000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34077220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34078000000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34079535000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34080300000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34083015000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34083660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34084065000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34084700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34085865000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34086585000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34087095000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34087635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34088325000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34089880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34089880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34089880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34089880000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34090660000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34092060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34092060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34092060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34092060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34092840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34094620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34094620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34094620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34094620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34095400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34096275000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34097040000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34097820000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34099365000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34100140000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34102845000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34103480000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34103865000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34104520000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34105695000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34106415000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34106955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34107645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34108155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34109700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34109700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34109700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34109700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34110480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34111900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34111900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34111900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34111900000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34112680000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34114440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34114440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34114440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34114440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34115220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34116105000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34116880000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34117660000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34119195000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34119960000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34122720000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34122980000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34123340000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34125500000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34125760000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34125940000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34126120000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34126960000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34127240000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34127440000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34127640000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34131615000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34132120000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34132200000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34132640000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34134465000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34136200000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34137380000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34137800000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34142360000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34142800000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34144700000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34145140000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34147300000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34147720000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34150245000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34150455000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34150940000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34151380000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34151800000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34152220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34153605000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34154060000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34154920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34155340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34157805000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34158260000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34159120000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34159200000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34160440000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34161640000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34162840000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34163260000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34163680000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34164460000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34165300000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34165720000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34167000000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34168080000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34168520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34169820000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34170705000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34171160000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34172020000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34172440000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34173560000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34178595000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34179100000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34179915000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34180420000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34181145000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34181740000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34183180000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34183340000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34183780000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34184560000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34185080000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34185840000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34186020000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34186460000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34187260000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34188700000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34189120000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34189540000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34190415000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34190860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34191615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34191945000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34192400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34193055000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34193240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34193680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34194460000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34195037000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34195220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34195660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34196440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34197195000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34197380000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34197820000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34198600000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34199235000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34199420000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34199860000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34200640000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34201275000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34201460000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34201900000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34202680000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34203555000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34203740000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34204180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34204960000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34205715000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34206045000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34206500000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34207155000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34207340000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34207780000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34208325000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34208520000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34208960000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34209760000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34212075000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34212260000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34212700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34213480000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34214385000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34214580000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34215020000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34215820000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34220625000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34220745000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34220865000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34221435000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34221585000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34221705000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34222275000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34222395000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34222935000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34223595000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34223745000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34224465000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34224585000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34225305000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34233135000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34233285000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34233465000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34233645000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34235475000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34252000000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34253040000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34257040000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34257760000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34258540000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34259380000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34260780000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34261560000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34266940000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34267800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34268680000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34270125000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34271800000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34272640000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34273680000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34274620000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34275220000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34315695000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34316300000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34316715000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34317340000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34318545000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34319265000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34319775000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34320315000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34321005000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34322560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34322560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34322560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34322560000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34323340000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34324740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34324740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34324740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34324740000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34325520000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34327300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34327300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34327300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34327300000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34328080000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34328955000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34329720000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34330500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34332045000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34332820000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34335555000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34336160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34336575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34337200000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34338405000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34339125000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34339635000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34340175000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34340865000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34342420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34342420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34342420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34342420000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34343200000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34344600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34344600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34344600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34344600000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34345380000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34347160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34347160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34347160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34347160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34347940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34348815000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34349580000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34350360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34351905000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34352680000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34355415000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34356020000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34356435000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34357060000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34358265000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34358985000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34359495000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34360035000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34360725000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34362280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34362280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34362280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34362280000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34363060000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34364460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34364460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34364460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34364460000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34365240000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34367020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34367020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34367020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34367020000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34367800000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34368675000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34369440000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34370220000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34371765000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34372540000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34375300000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34375560000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34375920000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34378080000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34378340000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34378520000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34378700000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34379540000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34379820000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34380020000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34380220000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34384185000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34384660000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34384740000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34385180000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34387005000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34388740000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34389920000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34390340000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34394900000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34395340000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34397240000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34397680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34399840000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34400260000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34402815000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34403055000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34403480000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34403920000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34404340000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34404760000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34406175000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34406620000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34407460000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34407880000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34410375000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34410820000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34411660000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34411740000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34412980000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34414180000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34415380000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34415800000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34416220000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34417000000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34417840000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34418260000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34419540000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34420620000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34421060000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34422360000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34423245000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34423700000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34424560000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34424980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34426100000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34431165000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34431680000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34432545000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34433060000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34433835000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34434440000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34435900000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34436060000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34436500000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34437280000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34437800000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34438560000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34438740000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34439180000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34439980000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34441420000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34441840000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34442260000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34443165000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34443620000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34444395000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34444725000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34445180000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34445835000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34446020000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34446460000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34447240000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34447847000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34448040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34448480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34449280000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34450035000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34450220000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34450660000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34451440000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34452075000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34452260000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34452700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34453480000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34454115000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34454300000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34454740000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34455520000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34456425000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34456620000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34457060000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34457860000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34458615000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34458945000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34459400000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34460055000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34460240000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34460680000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34461255000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34461440000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34461880000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34462660000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34464975000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34465160000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34465600000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34466380000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34467285000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34467480000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34467920000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34468720000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34473555000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34473705000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34473855000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34474425000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34474605000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34474755000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34475325000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34475475000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34476045000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34476765000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34476945000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34477695000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34477845000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34478595000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34486455000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34486635000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34486845000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34487055000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34488915000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34505460000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34506240000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34510240000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34510960000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34511740000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34512580000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34513980000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34514760000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34520140000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34521000000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34521880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34523325000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34525000000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34525840000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34526880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34527820000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34528420000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34568925000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34569500000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34569945000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34570540000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34571775000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34572525000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34573245000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34573935000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34574625000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34576320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34576320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34576320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34576320000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34577100000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34578520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34578520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34578520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34578520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34579300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34581060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34581060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34581060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34581060000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34581840000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34582725000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34583500000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34584280000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34585815000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34586580000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34589355000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34589940000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34590405000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34590980000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34592205000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34592955000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34593645000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34594365000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34595055000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34596760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34596760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34596760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34596760000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34597540000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34598940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34598940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34598940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34598940000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34599720000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34601500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34601500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34601500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34601500000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34602280000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34603155000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34603920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34604700000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34606245000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34607020000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34609785000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34610360000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34610805000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34611400000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34612635000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34613385000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34614105000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34614795000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34615485000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34617180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34617180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34617180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34617180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34617960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34619380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34619380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34619380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34619380000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34620160000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34621920000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34622700000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34623585000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34624360000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34625140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34626675000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34627440000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34630200000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34630460000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34630820000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34632980000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34633240000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34633420000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34633600000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34634440000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34634720000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34634920000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34635120000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34639095000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34639600000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34639680000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34640120000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34641945000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34643680000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34644860000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34645280000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34649840000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34650280000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34652180000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34652620000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34654780000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34655200000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34657785000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34658055000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34658680000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34659100000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34659520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34659940000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34661385000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34661840000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34662700000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34663120000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34665645000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34666100000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34666960000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34667040000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34668280000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34669480000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34670680000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34671100000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34671520000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34672300000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34673140000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34673560000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34674840000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34675920000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34676360000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34677660000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34678545000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34679000000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34679860000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34680280000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34681400000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34686495000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34687000000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34687875000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34688380000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34689165000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34689760000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34691200000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34691360000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34691800000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34692580000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34693100000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34693860000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34694040000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34694480000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34695280000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34696720000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34697140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34697560000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34698495000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34698940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34699695000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34700025000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34700480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34701135000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34701320000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34701760000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34702540000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34703177000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34703360000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34703800000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34704580000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34705335000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34705520000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34705960000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34706740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34707375000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34707560000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34708000000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34708780000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34709415000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34709600000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34710040000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34710820000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34711755000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34711940000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34712380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34713160000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34713915000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34714245000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34714700000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34715355000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34715540000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34715980000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34716585000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34716780000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34717220000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34718020000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34720335000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34720520000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34720960000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34721740000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34722645000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34722840000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34723280000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34724080000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34728945000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34729125000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34729305000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34729935000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34730145000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34730325000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34730955000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34731135000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34731735000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34732455000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34732665000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34733445000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34733625000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34734405000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34742295000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34742505000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34742745000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34742985000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34744875000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34761460000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34762500000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34766680000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34767400000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34768180000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34769020000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34770420000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34771200000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34776760000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34777800000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34778860000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34780305000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34782160000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34783000000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34784040000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34784980000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34785580000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34826115000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34826660000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34827135000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34827700000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34828965000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34829745000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34830435000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34831155000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34831845000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34833520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34833520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34833520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34833520000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34834300000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34835700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34835700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34835700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34835700000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34836480000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34838260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34838260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34838260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34838260000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34839040000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34839915000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34840680000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34841460000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34843005000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34843780000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34846575000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34847120000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34847595000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34848160000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34849425000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34850205000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34850895000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34851615000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34852305000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34853980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34853980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34853980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34853980000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34854760000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34856160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34856160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34856160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34856160000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34856940000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34858720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34858720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34858720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34858720000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34859500000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34860375000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34861140000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34861920000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34863465000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34864240000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34867035000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34867580000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34868055000Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34868620000Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34869885000Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34870665000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34871355000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34872075000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34872765000Test CAB MEMORY READ THROUGH WB SLAVE FROM PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34874440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34874440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34874440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34874440000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34875220000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34876620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34876620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34876620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34876620000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34877400000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34879180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34879180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34879180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34879180000Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34879960000Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34880835000Test I/O WRITE TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34881600000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34882380000Test I/O READ TRANSACTION FROM WB TO PCI TESTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34883925000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34884700000Test CHECK MAXIMUM IMAGE SIZEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34887460000Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34887720000Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34888080000Test ERRONEOUS CAB MEMORY READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34890240000Test ERRONEOUS I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34890500000Test ERRONEOUS I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34890680000Test CAB I/O WRITE TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34890860000Test CAB I/O READ TO WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34891700000Test ERRONEOUS WB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34891980000Test ERRONEOUS WB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34892180000Test WB CAB CONFIGURATION WRITE ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34892380000Test WB CAB CONFIGURATION READ ACCESSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34896345000Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34896820000Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34896900000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34897340000Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34899165000Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34900900000Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34902080000Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34902500000Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEMreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34907060000Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34907500000Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34909400000Test CHECK NORMAL READ AFTER ERROR TERMINATED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34909840000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34912000000Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34912420000Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34915035000Test TARGET ABORT ERROR ON SINGLE WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34915335000Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34915900000Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34916320000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34916740000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34917160000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34918635000Test TARGET ABORT ERROR ON CAB MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34919080000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34919920000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34920340000Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34922895000Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34923340000Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34924180000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34924260000Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34925500000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34926700000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34927900000Test TARGET ABORT DURING SINGLE MEMORY READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34928320000Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34928740000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34929520000Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34930360000Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34930780000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34932060000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34933140000Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34933580000Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34934880000Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34935765000Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34936220000Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34937080000Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34937500000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34938620000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34943745000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34944260000Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34945185000Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34945700000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34946535000Test MASTER WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34947140000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34948600000Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34948760000Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34949200000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34949980000Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34950500000Test CLEARANCE OF PARITY INTERRUPT STATUSESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34951260000Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34951440000Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34951880000Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34952680000Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34954120000Test MASTER READ TRANSACTION WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34954540000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34954960000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34955925000Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34956380000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34957155000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34957485000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34957940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34958595000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34958780000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34959220000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34960000000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34960667000Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34960860000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34961300000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34962100000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34962855000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34963040000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34963480000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34964260000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34964895000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34965080000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34965520000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34966300000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34966935000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34967120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34967560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34968340000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34969305000Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34969500000Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34969940000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34970740000Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34971495000Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34971825000Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34972280000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34972935000Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34973120000Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34973560000Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34974195000Test EXTERNAL WRITE WITH NO PARITY ERRORSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34974380000Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34974820000Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34975600000Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34977915000Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34978100000Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34978540000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34979320000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34980225000Test PARITY ERROR HANDLING ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34980420000Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34980860000Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34981660000Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34986555000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34986765000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34986975000Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTEDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34987605000Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRYreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34987845000Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34988055000Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34988685000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34988895000Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34989525000Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34990305000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34990545000Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34991355000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34991565000Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 34992375000Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35000295000Test FULL WRITE FIFO BURST RETRIED FIRST TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35000535000Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35000805000Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35001075000Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35002995000Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35019600000Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35020640000Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIMEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35024820000Test BURST READ WITH DISCONNECT ON FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35025540000Test BURST READ WITH DISCONNECT AFTER FIRSTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35026320000Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35027160000Test BURST READ WITH NORMAL TERMINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35028580000Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35029360000Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35034880000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35035920000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALIDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35036980000Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZEROreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35038425000Test LATENCY TIMER OPERATION ON PCI MASTER WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35040460000Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35041300000Test LATENCY TIMER OPERATION DURING MASTER READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35042340000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35043280000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35043880000Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35047640000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35048265000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35048720000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35050040000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35050605000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35051060000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35052420000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35053185000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35053640000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35057960000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35065425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35065880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35066820000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35067260000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35067780000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35068700000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35069140000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35069560000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35069980000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35070480000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35071125000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35071200000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35072200000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35072620000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35073120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35074340000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35074780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35075200000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35075620000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35076120000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35076765000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35076840000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35080160000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35082720000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35084840000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35087400000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35089720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35090140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35090220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35090980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35091400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35091480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35092240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35092660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35092740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35093500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35093920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35094000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35096200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35096620000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35096700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35097460000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35097880000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35097960000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35098720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35099140000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35099220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35099980000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35100400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35100480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35102680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35103880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35104300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35104380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35105140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35106340000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35106760000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35106840000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35107600000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35108800000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35109220000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35109300000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35110060000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35111260000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35111680000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35111760000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35113960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35115160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35115915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35115980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35116720000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35117920000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35118675000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35118740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35119480000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35120680000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35121435000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35121500000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35122240000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35123440000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35124195000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35124260000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35124705000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35125035000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35125365000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35125695000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35126025000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35126355000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35126685000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35129360000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35129985000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35130440000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35131760000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35132325000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35132780000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35134140000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35134905000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35135360000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35139680000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35147145000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35147600000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35148540000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35148980000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35149500000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35150420000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35150860000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35151280000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35151700000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35152200000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35152845000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35152920000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35153920000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35154340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35154840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35156060000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35156500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35156920000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35157340000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35157840000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35158485000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35158560000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35161880000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35164440000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35166560000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35169120000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35171440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35171860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35171940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35172700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35173120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35173200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35173960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35174380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35174460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35175220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35175640000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35175720000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35177920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35178340000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35178420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35179180000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35179600000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35179680000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35180440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35180860000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35180940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35181700000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35182120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35182200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35184400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35185600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35186020000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35186100000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35186860000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35188060000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35188480000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35188560000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35189320000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35190520000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35190940000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35191020000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35191780000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35192980000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35193400000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35193480000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35195680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35196880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35197635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35197700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35198440000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35199640000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35200395000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35200460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35201200000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35202400000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35203155000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35203220000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35203960000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35205160000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35205915000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35205980000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35206425000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35206755000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35207085000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35207415000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35207745000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35208075000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35208405000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35211080000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35211705000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35212160000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35213480000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35214045000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35214500000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35215860000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35216625000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35217080000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35221400000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35228865000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35229320000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35230260000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35230700000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35231220000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35232140000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35232580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35233000000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35233420000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35233920000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35234565000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35234640000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35235640000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35236060000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35236560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35237780000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35238220000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35238640000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35239060000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35239560000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35240205000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35240280000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35243600000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35246160000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35248280000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35250840000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35253160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35253580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35253660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35254420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35254840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35254920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35255680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35256100000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35256180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35256940000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35257360000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35257440000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35259640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35260060000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35260140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35260900000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35261320000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35261400000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35262160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35262580000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35262660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35263420000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35263840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35263920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35266120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35267320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35267740000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35267820000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35268580000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35269780000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35270200000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35270280000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35271040000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35272240000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35272660000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35272740000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35273500000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35274700000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35275120000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35275200000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35277400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35278600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35279355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35279420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35280160000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35281360000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35282115000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35282180000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35282920000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35284120000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35284875000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35284940000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35285680000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35286880000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35287635000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35287700000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35288145000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35288475000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35288805000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35289135000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35289465000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35289795000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35290125000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35292800000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35293425000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35293880000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35295200000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35295765000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35296220000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35297580000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35298345000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35298800000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35303120000Test NORMAL POSTED WRITE THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35310585000Test NORMAL MEMORY READ THROUGH PCI TARGET UNITreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35311040000Test PCI ERROR STATUS AFTER NORMAL WRITE/READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35311980000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35312420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35312940000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35313860000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON FIRST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35314300000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35314720000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35315140000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35315640000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35316285000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35316360000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35317360000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35317780000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35318280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35319500000Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFERreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35319940000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERRORreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35320360000Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35320780000Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35321280000Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35321925000Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WBreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35322000000Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEAREDreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35325320000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35327880000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35330000000Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35332560000Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35334880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35335300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35335380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35336140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35336560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35336640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35337400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35337820000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35337900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35338660000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35339080000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35339160000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35341360000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35341780000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35341860000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35342620000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35343040000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35343120000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35343880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35344300000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35344380000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35345140000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35345560000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35345640000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35347840000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35349040000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35349460000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35349540000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35350300000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35351500000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35351920000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35352000000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35352760000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35353960000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35354380000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35354460000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35355220000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35356420000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35356840000Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35356920000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35359120000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35360320000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35361075000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35361140000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35361880000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35363080000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35363835000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35363900000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35364640000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35365840000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35366595000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35366660000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35367400000Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35368600000Test ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35369355000Test CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35369420000Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35369865000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - IACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35370195000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - SPECIALreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35370525000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED0reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35370855000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED1reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35371185000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED2reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35371515000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - RESERVED3reported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35371845000Test MASTER ABORT WHEN ACCESSING TARGET WITH UNSUPPORTED BUS COMMAND - DUAL_ADDR_CYCreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35374755000Test SINGLE READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35375595000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35376040000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35376525000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35377395000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35377840000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35378325000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON FIRST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35379195000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35379640000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35380185000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON SECOND DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35381055000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35381500000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35382105000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35382975000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35383420000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35384055000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON ONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35384895000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35385340000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35386095000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE ON LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35386935000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35387380000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35388165000Test FULL FIFO BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE BEFORE LAST DATAPHASEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35389035000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35389480000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35390055000Test BURST READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONE, ERROR NOT PULLED OUT ON PCIreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35390500000Test ALL PCI DEVICE STATUSES AFTER ERRONEOUS TARGET READSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35393295000Test SINGLE I/O READ THROUGH PCI TARGET TERMINATED WITH ERROR ON WISHBONEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35394135000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35394580000Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER READ THROUGH TARGET TERMINATED WITH TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35401100000Test FAST BACK TO BACK THROUGH TARGET - FILL WRITE FIFO, CHECK RETRY ON FAST B2B WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35404280000Test FAST BACK TO BACK THROUGH TARGET - BOTH WRITES SMALL ENOUGH TO PROCEEDE THROUGH FIFOreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35411020000Test FAST BACK TO BACK THROUGH TARGET - FIRST WRITE FULL FIFO, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35414600000Test FAST BACK TO BACK THROUGH TARGET - TWO SINGLE IO WRITESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35415285000Test FAST BACK TO BACK THROUGH TARGET - FIRST I/O WRITE, THEN READ BACKreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35420560000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35423840000Test TARGET DISCONNECT WHEN WRITE FIFO FILLED DURING BURST WRITEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35424585000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35425185000Test TARGET DISCONNECT WHEN READ FIFO IS EMPTIED DURING BURST READreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35425560000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35425800000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35426040000Test TARGET DISCONNECT ON WRITES WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35426655000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35427195000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35427735000Test TARGET DISCONNECT ON READS WITH UNSUPPORTED WRAPING MODESreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35430080000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35430320000Test TARGET DISCONNECT ON BURST WRITE TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35430945000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35431485000Test TARGET DISCONNECT ON BURST READ TO IO SPACEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35433435000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35433615000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35433825000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434035000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434215000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434425000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434635000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434815000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35434995000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35435175000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35435385000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35435595000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35435805000Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATIONreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35436615000Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORTreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35437060000Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTSreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35442465000Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35445045000Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35446240000Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVEreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35450840000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGETreported *SUCCESSFULL*!**********************************************************************************************************************************************************************************At time 35453520000Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVEreported *SUCCESSFULL*!************************************************************************************************************************ PCI Testcase summary *******************************Tests performed: 36000Failed tests : 0Successfull tests: 36000******************************* PCI Testcase summary *******************************